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    MEMORY SYSTEM TESTER USING TEST PAD REAL TIME MONITORING
    1.
    发明申请
    MEMORY SYSTEM TESTER USING TEST PAD REAL TIME MONITORING 有权

    公开(公告)号：US20220101938A1

    公开(公告)日：2022-03-31

    申请号：US17549377

    申请日：2021-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Vigilante ,  Gianluca Scalisi ,  Andrea Pozzato ,  Andrea Salvioni ,  Mauro Luigi Sali

    IPC: G11C29/38 ,  G11C29/36 ,  G11C16/04

    Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

    READ TRAINING FOR NON-VOLATILE MEMORY
    3.
    发明公开
    READ TRAINING FOR NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20240184455A1

    公开(公告)日：2024-06-06

    申请号：US18513291

    申请日：2023-11-17

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Vigilante ,  Riccardo Muzzetto

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Methods, systems, and devices for read training for non-volatile memory are described. In some examples, a memory system may perform read training by receiving a read command and reading a first subset of data. The memory system may apply one or more delays to each byte of the first subset of data and may select a delay for reading a second subset of data. Upon selecting the delay, the memory system may read the second subset of data using the selected delay.

    Managed-NAND real time analyzer and method
    4.
    发明授权
    Managed-NAND real time analyzer and method 有权

    公开(公告)号：US11495317B2

    公开(公告)日：2022-11-08

    申请号：US16453712

    申请日：2019-06-26

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Vigilante ,  Gianluca Scalisi

    IPC: G11C29/18 ,  G06F13/16 ,  G11C29/16 ,  G06F12/02

    Abstract: A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.

    Interconnect system
    6.
    发明授权
    Interconnect system 有权

    公开(公告)号：US10957418B1

    公开(公告)日：2021-03-23

    申请号：US16550510

    申请日：2019-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Vigilante

    IPC: H01L23/48 ,  G11C29/56 ,  G06F13/16 ,  G06F13/10 ,  H01R12/71 ,  G01R1/067 ,  G01R31/317 ,  G11C16/04

    Abstract: A variety of applications can include a system having a system platform to which a memory system can be attached for operation of the system. With the memory system removed from the system platform or before being attached to the system platform, an interposer can be connected at the location for the memory system on the system platform to facilitate testing of the system with respect to the memory system. The interposer can include a set of electrical connectors embedded on a first side of the interposer to connect to the system platform and a connector embedded on a second side of the interposer opposite the first side, where the connector allows coupling to an external platform to convey signals between the system platform and the external platform. Additional apparatus, systems, and methods are disclosed.

    MULTICHIP MEMORY PACKAGE WITH INTERNAL CHANNEL
    8.
    发明申请
    MULTICHIP MEMORY PACKAGE WITH INTERNAL CHANNEL 有权

    公开(公告)号：US20210233585A1

    公开(公告)日：2021-07-29

    申请号：US16776402

    申请日：2020-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Vigilante ,  David A. Palmer

    IPC: G11C14/00 ,  G06F3/06 ,  G06F13/16 ,  G06F11/10

    Abstract: Methods, systems, and devices for multichip memory packages are described. A multichip memory package may include at least two dies that include different types of memory, such as one die that includes non-volatile memory and another die that includes volatile memory. The package may include an in-package channel that supports internal data transfer between the two types of memory. For example, a respective controller for each of the types of memory may also be included in the package and may be coupled with each other via the in-package interface. In some cases, data may be read from one of the types of memory and written to the other type of memory in response to a single read or write command and without passing over any interface outside of the package.

    INTERCONNECT SYSTEM
    9.
    发明申请
    INTERCONNECT SYSTEM 有权

    公开(公告)号：US20210065838A1

    公开(公告)日：2021-03-04

    申请号：US16550510

    申请日：2019-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Vigilante

    IPC: G11C29/56 ,  G06F13/16 ,  G06F13/10 ,  H01R12/71 ,  G01R1/067 ,  G01R31/317

    Abstract: A variety of applications can include a system having a system platform to which a memory system can be attached for operation of the system. With the memory system removed from the system platform or before being attached to the system platform, an interposer can be connected at the location for the memory system on the system platform to facilitate testing of the system with respect to the memory system. The interposer can include a set of electrical connectors embedded on a first side of the interposer to connect to the system platform and a connector embedded on a second side of the interposer opposite the first side, where the connector allows coupling to an external platform to convey signals between the system platform and the external platform. Additional apparatus, systems, and methods are disclosed.

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