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    CROSSTALK CANCELLATION FOR SIGNAL LINES
    1.
    发明公开
    CROSSTALK CANCELLATION FOR SIGNAL LINES 审中-公开

    公开(公告)号：US20240260171A1

    公开(公告)日：2024-08-01

    申请号：US18632122

    申请日：2024-04-10

    Applicant: Micron Technology, Inc.

    Inventor： M. Ataul Karim ,  David K. Ovard ,  Aparna U. Limaye ,  Timothy M. Hollis

    IPC: H05K1/02 ,  H04B3/32 ,  H04B3/487

    CPC classification number: H05K1/0233 ,  H04B3/32 ,  H04B3/487 ,  H05K1/0228

    Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

    Apparatuses including ball grid arrays and associated systems
    3.
    发明授权
    Apparatuses including ball grid arrays and associated systems 有权

    公开(公告)号：US12300597B2

    公开(公告)日：2025-05-13

    申请号：US18652515

    申请日：2024-05-01

    Applicant: Micron Technology, Inc.

    Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

    Abstract: Systems may include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device may be connected to the CPU, the GPU, or the FPGA. The memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.

    CROSSTALK CANCELLATION FOR SIGNAL LINES
    4.
    发明申请
    CROSSTALK CANCELLATION FOR SIGNAL LINES 有权

    公开(公告)号：US20220346220A1

    公开(公告)日：2022-10-27

    申请号：US17238797

    申请日：2021-04-23

    Applicant: Micron Technology, Inc.

    Inventor： M. Ataul Karim ,  David K. Ovard ,  Aparna U. Limaye ,  Timothy M. Hollis

    IPC: H05K1/02 ,  H04B3/487 ,  H04B3/32

    Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

    Enhanced performance memory systems and methods
    5.
    发明授权
    Enhanced performance memory systems and methods 有权
    增强的性能内存系统和方法

    公开(公告)号：US09154131B2

    公开(公告)日：2015-10-06

    申请号：US13796410

    申请日：2013-03-12

    Applicant: Micron Technology, Inc.

    Inventor： Roy E. Greeff ,  David K. Ovard

    IPC: G11C5/06 ,  H03K19/003 ,  G06F13/40

    CPC classification number: H03K19/003 ,  G06F13/4086

    Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.

    Abstract translation: 公开了包括用于操作这种存储器系统的存储器系统和方法的数字存储器件和系统。 在实施例中，存储器系统可以包括通信地耦合到处理器的处理器和存储器控制器。 存储器总线通过存储器总线与至少两个存储器单元进行通信。 至少一个除法器单元可以插入在存储器总线和至少两个存储器单元之间，该至少两个存储器单元被配置为在将存储器总线的阻抗与存储器单元的阻抗匹配的同时大致相等地分配接收信号的电平。

    APPARATUSES INCLUDING BALL GRID ARRAYS AND ASSOCIATED SYSTEMS
    6.
    发明申请
    APPARATUSES INCLUDING BALL GRID ARRAYS AND ASSOCIATED SYSTEMS 有权

    公开(公告)号：US20250157909A1

    公开(公告)日：2025-05-15

    申请号：US19022030

    申请日：2025-01-15

    Applicant: Micron Technology, Inc.

    Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

    IPC: H01L23/498 ,  H01L23/00

    Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal is located laterally or longitudinally adjacent to no more than two other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.

    Crosstalk cancellation for signal lines
    7.
    发明授权
    Crosstalk cancellation for signal lines 有权

    公开(公告)号：US11979979B2

    公开(公告)日：2024-05-07

    申请号：US17238797

    申请日：2021-04-23

    Applicant: Micron Technology, Inc.

    Inventor： M. Ataul Karim ,  David K. Ovard ,  Aparna U. Limaye ,  Timothy M. Hollis

    IPC: H05K1/02 ,  H04B3/32 ,  H04B3/487

    CPC classification number: H05K1/0233 ,  H04B3/32 ,  H04B3/487 ,  H05K1/0228

    Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

    BALL GRID ARRAYS AND ASSOCIATED APPARATUSES AND SYSTEMS
    8.
    发明申请
    BALL GRID ARRAYS AND ASSOCIATED APPARATUSES AND SYSTEMS 有权

    公开(公告)号：US20210375738A1

    公开(公告)日：2021-12-02

    申请号：US17334447

    申请日：2021-05-28

    Applicant: Micron Technology, Inc.

    Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

    Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

    ENHANCED PERFORMANCE MEMORY SYSTEMS AND METHODS
    10.
    发明申请
    ENHANCED PERFORMANCE MEMORY SYSTEMS AND METHODS 有权

    公开(公告)号：US20130187679A1

    公开(公告)日：2013-07-25

    申请号：US13796410

    申请日：2013-03-12

    Applicant: Micron Technology, Inc.

    Inventor： Roy E. Greeff ,  David K. Ovard

    IPC: H03K19/003

    CPC classification number: H03K19/003 ,  G06F13/4086

    Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.

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