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公开(公告)号：US20210183448A1
公开(公告)日：2021-06-17
申请号：US16714369
申请日：2019-12-13
Applicant: Micron Technology, Inc.
Inventor： Ji-Hye Shin , Foroozan S. Koushan , Tomoko Iwasaki , Jayasree Nayar
Abstract: A logic state to be stored at a memory cell of a memory device is determined, where the logic state is to be represented by a threshold voltage stored at the memory cell. A verify reference voltage associated with the logic state is determined. The verify reference voltage defines a target voltage level of the threshold voltage associated with the logic state. The verify reference voltage is updated using an amount of compensation for an expected shift in the threshold voltage of the memory cell after heat is applied to the memory device. Before the heat is applied to the memory device, a plurality of sets of multiple programming pulses to the memory cell is applied until a threshold condition is satisfied. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell to the updated verify reference voltage.
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公开(公告)号：US11423990B2
公开(公告)日：2022-08-23
申请号：US16947642
申请日：2020-08-11
Applicant: Micron Technology, Inc.
Inventor： Foroozan S. Koushan , Shinji Sato
Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.
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Patent Agency Ranking
公开(公告)号：US11646083B2
公开(公告)日：2023-05-09
申请号：US17868703
申请日：2022-07-19
Applicant: Micron Technology, Inc.
Inventor： Foroozan S. Koushan , Shinji Sato
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/32
Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.
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公开(公告)号：US20210343346A1
公开(公告)日：2021-11-04
申请号：US17373701
申请日：2021-07-12
Applicant: Micron Technology, Inc.
Inventor： Ji-Hye Shin , Foroozan S. Koushan , Tomoko Iwasaki , Jayasree Nayar
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.
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公开(公告)号：US11735267B2
公开(公告)日：2023-08-22
申请号：US17373701
申请日：2021-07-12
Applicant: Micron Technology, Inc.
Inventor： Ji-Hye Shin , Foroozan S. Koushan , Tomoko Iwasaki , Jayasree Nayar
CPC classification number: G11C16/12 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/3459 , G11C16/26
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.
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公开(公告)号：US20220351782A1
公开(公告)日：2022-11-03
申请号：US17868703
申请日：2022-07-19
Applicant: Micron Technology, Inc.
Inventor： Foroozan S. Koushan , Shinji Sato
Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.
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公开(公告)号：US11069412B2
公开(公告)日：2021-07-20
申请号：US16714369
申请日：2019-12-13
Applicant: Micron Technology, Inc.
Inventor： Ji-Hye Shin , Foroozan S. Koushan , Tomoko Iwasaki , Jayasree Nayar
Abstract: A logic state to be stored at a memory cell of a memory device is determined, where the logic state is to be represented by a threshold voltage stored at the memory cell. A verify reference voltage associated with the logic state is determined. The verify reference voltage defines a target voltage level of the threshold voltage associated with the logic state. The verify reference voltage is updated using an amount of compensation for an expected shift in the threshold voltage of the memory cell after heat is applied to the memory device. Before the heat is applied to the memory device, a plurality of sets of multiple programming pulses to the memory cell is applied until a threshold condition is satisfied. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell to the updated verify reference voltage.
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