公开(公告)号：US20250078948A1

公开(公告)日：2025-03-06

申请号：US18952806

申请日：2024-11-19

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G11C29/42 ,  G11C7/06 ,  G11C7/10 ,  G11C29/12

Abstract: Methods, systems, and devices for techniques for initializing memory error correction are described. A memory system may perform operations relating to writing data to multiple memory cells belonging to one or more rows of the memory system in response to a single write command. For example, the memory system may receive (e.g., from a host system) an activation command (e.g., a row group activation command) indicating a row group address. The memory system may activate a set of rows indicated by the row group address. In response to a write command (e.g., a row group write command), the memory system may write data in a respective memory cell of each row indicated by the row group address. For example, each memory cell to be written may correspond to a column address included in the write command. The memory system may write a same logic state to each memory cell.

公开(公告)号：US12211573B2

公开(公告)日：2025-01-28

申请号：US17725025

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G11C29/12 ,  G11C29/18 ,  G11C29/36 ,  G11C29/46 ,  G11C29/56

Abstract: Systems and methods for filtering data (DQ) signals are described herein. The systems and methods may involve operating a memory to enter a training mode and sending a command to a decoder while the memory is in the training mode. The decoder may generate a command/address waveform in response to the command. The systems and methods may involve transmitting a burst indicator waveform via a first pin of the memory. The burst indicator waveform may be generated by a burst indicator generator of the memory based on the command/address waveform.

公开(公告)号：US20230039002A1

公开(公告)日：2023-02-09

申请号：US17939801

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G06F11/10

Abstract: Methods, systems, and devices for techniques for memory error correction are described. A memory device may operate cycles associated with refresh operations and cycles associated with refresh with error correction (ECC) operations independently. For example, the memory device may include an ECC patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. Additionally, the memory device may include a refresh counter which indicates a row on which to perform a refresh operation. In response to receiving a command of a first, the memory device may modify the error correction counter and maintain the refresh counter. Alternatively, in response to receiving a command of a second, the memory device may modify the refresh counter and maintain the error correction counter.

公开(公告)号：US12124333B2

公开(公告)日：2024-10-22

申请号：US17939801

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G06F11/10

CPC classification number: G06F11/1096

Abstract: Methods, systems, and devices for techniques for memory error correction are described. A memory device operates in cycles associated with refresh operations and in cycles associated with refresh with error correction (ECC) operations independently. For example, the memory device includes an ECC patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. Additionally, the memory device may include a refresh counter which indicates a row on which to perform a refresh operation. In response to receiving a command of a first type, the memory device modifies the error correction counter and maintains the refresh counter. Alternatively, in response to receiving a command of a second type, the memory device modifies the refresh counter and maintains the error correction counter.

公开(公告)号：US11868661B2

公开(公告)日：2024-01-09

申请号：US17746767

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G06F3/06 ,  G11C11/406 ,  G11C11/408

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/406 ,  G11C11/408

Abstract: An apparatus having counters for sub-addresses in segments of row address to count activation commands applied to row addresses including the sub-addresses. The counters are configured to count activation commands applied to row addresses containing the sub-addresses in accessing rows of memory cells in a memory device; For example, in response to an activation command applied to a row address having first sub-addresses, counts stored in a portion of the counters corresponding to the first sub-addresses are increased for the count of the activation command. For each respective segment, counts stored in counters for sub-addresses in the respective segment are used to determine whether at least one of the sub-addresses has seen more activation commands than a threshold. An alert is generated for risk mitigation operations in response to each segment having at least one sub-address that has seen more activation commands than the threshold.

公开(公告)号：US20250103434A1

公开(公告)日：2025-03-27

申请号：US18908370

申请日：2024-10-07

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G06F11/10

Abstract: Methods, systems, and devices for techniques for memory error correction are described. A memory device may operate cycles associated with refresh operations and cycles associated with refresh with error correction (ECC) operations independently. For example, the memory device may include an ECC patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. Additionally, the memory device may include a refresh counter which indicates a row on which to perform a refresh operation. In response to receiving a command of a first, the memory device may modify the error correction counter and maintain the refresh counter. Alternatively, in response to receiving a command of a second, the memory device may modify the refresh counter and maintain the error correction counter.

公开(公告)号：US12170122B2

公开(公告)日：2024-12-17

申请号：US17740823

申请日：2022-05-10

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C29/12 ,  G11C29/42

Abstract: Methods, systems, and devices for techniques for initializing memory error correction are described. A memory system may perform operations relating to writing data to multiple memory cells belonging to one or more rows of the memory system in response to a single write command. For example, the memory system may receive (e.g., from a host system) an activation command (e.g., a row group activation command) indicating a row group address. The memory system may activate a set of rows indicated by the row group address. In response to a write command (e.g., a row group write command), the memory system may write data in a respective memory cell of each row indicated by the row group address. For example, each memory cell to be written may correspond to a column address included in the write command. The memory system may write a same logic state to each memory cell.

公开(公告)号：US20240061619A1

公开(公告)日：2024-02-22

申请号：US18501897

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G06F3/06 ,  G11C11/406 ,  G11C11/408

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/406 ,  G11C11/408

Abstract: An apparatus having counters for sub-addresses in segments of row address to count activation commands applied to row addresses including the sub-addresses. The counters are configured to count activation commands applied to row addresses containing the sub-addresses in accessing rows of memory cells in a memory device; For example, in response to an activation command applied to a row address having first sub-addresses, counts stored in a portion of the counters corresponding to the first sub-addresses are increased for the count of the activation command. For each respective segment, counts stored in counters for sub-addresses in the respective segment are used to determine whether at least one of the sub-addresses has seen more activation commands than a threshold. An alert is generated for risk mitigation operations in response to each segment having at least one sub-address that has seen more activation commands than the threshold.

公开(公告)号：US20230376241A1

公开(公告)日：2023-11-23

申请号：US17746767

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G06F3/06 ,  G11C11/406 ,  G11C11/408

CPC classification number: G06F3/0659 ,  G11C11/406 ,  G11C11/408 ,  G06F3/0604 ,  G06F3/0679

Abstract: An apparatus having counters for sub-addresses in segments of row address to count activation commands applied to row addresses including the sub-addresses. The counters are configured to count activation commands applied to row addresses containing the sub-addresses in accessing rows of memory cells in a memory device; For example, in response to an activation command applied to a row address having first sub-addresses, counts stored in a portion of the counters corresponding to the first sub-addresses are increased for the count of the activation command. For each respective segment, counts stored in counters for sub-addresses in the respective segment are used to determine whether at least one of the sub-addresses has seen more activation commands than a threshold. An alert is generated for risk mitigation operations in response to each segment having at least one sub-address that has seen more activation commands than the threshold.

公开(公告)号：US20230368856A1

公开(公告)日：2023-11-16

申请号：US17740823

申请日：2022-05-10

Applicant: Micron Technology , Inc.

Inventor： Kai Wang

IPC: G11C29/42 ,  G11C29/12 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/12015 ,  G11C7/1048 ,  G11C7/06

Abstract: Methods, systems, and devices for techniques for initializing memory error correction are described. A memory system may perform operations relating to writing data to multiple memory cells belonging to one or more rows of the memory system in response to a single write command. For example, the memory system may receive (e.g., from a host system) an activation command (e.g., a row group activation command) indicating a row group address. The memory system may activate a set of rows indicated by the row group address. In response to a write command (e.g., a row group write command), the memory system may write data in a respective memory cell of each row indicated by the row group address. For example, each memory cell to be written may correspond to a column address included in the write command. The memory system may write a same logic state to each memory cell.