公开(公告)号：US20240126434A1

公开(公告)日：2024-04-18

申请号：US18390820

申请日：2023-12-20

Applicant: Micron Technology, Inc.

Inventor： Eric V. Pohlmann ,  Neal J. Koyle

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0655 ,  G06F3/0683

Abstract: Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.

公开(公告)号：US12229406B2

公开(公告)日：2025-02-18

申请号：US18390820

申请日：2023-12-20

Applicant: Micron Technology, Inc.

Inventor： Eric V. Pohlmann ,  Neal J. Koyle

IPC: G06F3/06

Abstract: Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.

公开(公告)号：US11776600B2

公开(公告)日：2023-10-03

申请号：US17649006

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Erik V. Pohlmann ,  Neal J. Koyle

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/18

Abstract: Methods, systems, and devices for memory clock management and estimation procedures are described. A host device may determine a quantity of clock cycles associated with a duration for accessing a memory cell of a memory array based on truncating a value of a first parameter associated with another duration for a clock to perform a clock cycle. The host device may estimate a value of a second parameter related to (e.g., inversely proportional) to the truncated value of the first parameter and related to (e.g., directly proportional) to a correction factor, and may adjust (e.g., truncate) a third parameter to determine the quantity of clock cycles. Additionally or alternatively, the host device may adjust (e.g., perform a ceiling operation on) the second parameter to determine the quantity of clock cycles. The host device may access the memory cell based on the quantity of clock cycles.

公开(公告)号：US12197766B2

公开(公告)日：2025-01-14

申请号：US17517107

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather ,  Neal J. Koyle

IPC: G06F11/08 ,  G06F3/06 ,  G06F11/10 ,  G11C29/00

Abstract: Methods for operating a memory system are disclosed herein. In one embodiment, a method comprises receiving first data to be written at a logical address of a memory array, storing the first data at a first physical address corresponding to the logical address, and remapping the logical address to a second physical address, for example, using a soft post package repair operation. The method can further include receiving second data different from the first data to be written at the logical address, storing the second data at the second physical address, and remapping the logical address to the first physical address. In some embodiments, the method can comprise storing first and second ECC data corresponding to the first and second data, respectively. The method can further comprise outputting the first data and/or the second ECC data in response to a read request corresponding to the logical address.

公开(公告)号：US20220147267A1

公开(公告)日：2022-05-12

申请号：US17517107

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather ,  Neal J. Koyle

IPC: G06F3/06

Abstract: Methods for operating a memory system are disclosed herein. In one embodiment, a method comprises receiving first data to be written at a logical address of a memory array, storing the first data at a first physical address corresponding to the logical address, and remapping the logical address to a second physical address, for example, using a soft post package repair operation. The method can further include receiving second data different from the first data to be written at the logical address, storing the second data at the second physical address, and remapping the logical address to the first physical address. In some embodiments, the method can comprise storing first and second ECC data corresponding to the first and second data, respectively. The method can further comprise outputting the first data and/or the second ECC data in response to a read request corresponding to the logical address.

公开(公告)号：US11886702B2

公开(公告)日：2024-01-30

申请号：US17585253

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Eric V. Pohlmann ,  Neal J. Koyle

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0655 ,  G06F3/0683

Abstract: Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.

公开(公告)号：US20220246188A1

公开(公告)日：2022-08-04

申请号：US17649006

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Erik V. Pohlmann ,  Neal J. Koyle

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: Methods, systems, and devices for memory clock management and estimation procedures are described. A host device may determine a quantity of clock cycles associated with a duration for accessing a memory cell of a memory array based on truncating a value of a first parameter associated with another duration for a clock to perform a clock cycle. The host device may estimate a value of a second parameter related to (e.g., inversely proportional) to the truncated value of the first parameter and related to (e.g., directly proportional) to a correction factor, and may adjust (e.g., truncate) a third parameter to determine the quantity of clock cycles. Additionally or alternatively, the host device may adjust (e.g., perform a ceiling operation on) the second parameter to determine the quantity of clock cycles. The host device may access the memory cell based on the quantity of clock cycles.

公开(公告)号：US20220244860A1

公开(公告)日：2022-08-04

申请号：US17585253

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Eric V. Pohlmann ,  Neal J. Koyle

IPC: G06F3/06

Abstract: Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.