PROGRESSIVE EFFORT DECODER ARCHITECTURE
    2.
    发明申请
    PROGRESSIVE EFFORT DECODER ARCHITECTURE 有权
    进步的解码器架构

    公开(公告)号:US20160094247A1

    公开(公告)日:2016-03-31

    申请号:US14502513

    申请日:2014-09-30

    Abstract: A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.

    Abstract translation: 存储器设备可以包括用于存储数据的存储器组件。 存储器设备还可以包括可解码与数据相关联的码字的处理器。 处理器可以接收码字并且使用BCH解码器来确定码字是否可独立解码。 然后当使用BCH解码器确定码字可独立地解码时,处理器可以使用BCH解码器对码字进行解码。 否则,当码字未被确定为可以使用BCH解码器独立地解码时,处理器可以使用第二解码器和BCH解码器解码码字。

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