公开(公告)号：US11520240B2

公开(公告)日：2022-12-06

申请号：US17314410

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  G01R33/07 ,  H01L23/544

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

公开(公告)号：US11251096B2

公开(公告)日：2022-02-15

申请号：US16122106

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  H01L21/66 ,  H01L23/544 ,  H01L21/302

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

公开(公告)号：US10600681B2

公开(公告)日：2020-03-24

申请号：US16164542

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11556

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

公开(公告)号：US20190206726A1

公开(公告)日：2019-07-04

申请号：US16164542

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

公开(公告)号：US20220108927A1

公开(公告)日：2022-04-07

申请号：US17644414

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: H01L21/66 ,  H01L23/544 ,  H01L21/302 ,  H01L21/68

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

公开(公告)号：US11009798B2

公开(公告)日：2021-05-18

申请号：US16122062

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  G01R33/07 ,  H01L23/544

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

公开(公告)号：US20200073257A1

公开(公告)日：2020-03-05

申请号：US16122062

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  H01L23/544 ,  G01R33/07

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

公开(公告)号：US10147638B1

公开(公告)日：2018-12-04

申请号：US15858072

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

公开(公告)号：US12230546B2

公开(公告)日：2025-02-18

申请号：US17644414

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: H01L21/66 ,  G03F7/00 ,  H01L21/302 ,  H01L21/68 ,  H01L23/544

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

公开(公告)号：US11189526B2

公开(公告)日：2021-11-30

申请号：US16799223

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L27/11575 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11556

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.