公开(公告)号：US11955461B2

公开(公告)日：2024-04-09

申请号：US17410327

申请日：2021-08-24

Applicant: Micron Technology, Inc.

Inventor： Shiro Uchiyama

IPC: H01L25/065 ,  H01L21/50 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L23/544 ,  H01L25/50

Abstract: Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.

公开(公告)号：US20200035597A1

公开(公告)日：2020-01-30

申请号：US16590039

申请日：2019-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shiro Uchiyama

IPC: H01L23/522 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L27/108

Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.

公开(公告)号：US20240234378A1

公开(公告)日：2024-07-11

申请号：US18614583

申请日：2024-03-22

Applicant: Micron Technology, Inc.

Inventor： Shiro Uchiyama

IPC: H01L25/065 ,  H01L21/50 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L23/544 ,  H01L25/50

Abstract: Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.

公开(公告)号：US20230215828A1

公开(公告)日：2023-07-06

申请号：US17823638

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Andreas Kuesel ,  Takamasa Suzuki ,  Jens Polney ,  Seiji Narui ,  Shiro Uchiyama

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L25/0657 ,  H01L24/16 ,  H01L25/50 ,  H01L24/08 ,  H01L2225/06513 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/09179 ,  H01L2224/09133 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2224/16145 ,  H01L2224/09515 ,  H01L2224/09153 ,  H01L2224/08056 ,  H01L2924/30105 ,  H01L2225/06593 ,  H01L2225/06544

Abstract: Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.

公开(公告)号：US10600770B2

公开(公告)日：2020-03-24

申请号：US15978778

申请日：2018-05-14

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Shiro Uchiyama

IPC: G11C5/02 ,  H01L25/18 ,  H01L25/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/538

Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.

公开(公告)号：US20190385996A1

公开(公告)日：2019-12-19

申请号：US16553698

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Shiro Uchiyama

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L23/367

Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.

公开(公告)号：US09997452B1

公开(公告)日：2018-06-12

申请号：US15418568

申请日：2017-01-27

Applicant: Micron Technology, Inc.

Inventor： Shiro Uchiyama

IPC: H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L23/5226 ,  H01L21/762 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/10802 ,  H01L27/10897 ,  H01L29/0649

Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.

公开(公告)号：US20230065325A1

公开(公告)日：2023-03-02

申请号：US17589472

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Shiro Uchiyama ,  Eiichi Nakano

IPC: H01L23/544 ,  H01L23/48

Abstract: A semiconductor device assembly including a first semiconductor wafer having a first side and a second side opposite the first side, the first semiconductor wafer including: a first plurality of semiconductor devices at the first side, a plurality of non-metallic vias extending from the second side towards the first side, and a plurality of alignment marks, each vertically aligned with a corresponding one or more of the plurality of non-metallic vias, a second semiconductor wafer including a second plurality of semiconductor devices and a plurality of registration marks, each of the plurality of registration marks vertically aligned with a corresponding one or more of the plurality of alignment marks.

公开(公告)号：US10896875B2

公开(公告)日：2021-01-19

申请号：US16590039

申请日：2019-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shiro Uchiyama

IPC: H01L23/522 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L27/108

Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.

公开(公告)号：US10438888B2

公开(公告)日：2019-10-08

申请号：US16000697

申请日：2018-06-05

Applicant: Micron Technology, Inc.

Inventor： Shiro Uchiyama

IPC: H01L23/552 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L27/108

Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.