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    SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING
    1.
    发明申请
    SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING 有权

    公开(公告)号：US20250013258A1

    公开(公告)日：2025-01-09

    申请号：US18749057

    申请日：2024-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Fabien Funfrock ,  Elena Cabrera Bernal ,  Suhas Shivapakash ,  Jens Polney

    IPC: G06F1/08 ,  G06F3/06

    Abstract: Methods, systems, and devices for techniques for clock doubling are described. A clock adjustment circuit may receive as inputs two clock signals that each have the same frequency and different phases and may generate a clock signal with a higher frequency than the two clock signal inputs. A duty cycle monitor may monitor and support correction of a shift in the relative phases of the two input clocks to maintain a consistent duty cycle of the generated higher frequency clock signal. The clock adjustment circuit may reduce the length of a clock tree that is traversed by the higher frequency clock, such as to reduce bias temperature instability degradation or other types of signal degradation.

    Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device
    3.
    发明授权
    Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device 有权

    公开(公告)号：US10943627B2

    公开(公告)日：2021-03-09

    申请号：US16379585

    申请日：2019-04-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jens Polney

    IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

    Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command. buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.

    Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device
    7.
    发明授权
    Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device 有权

    公开(公告)号：US10297298B2

    公开(公告)日：2019-05-21

    申请号：US15730552

    申请日：2017-10-11

    Applicant: Micron Technology, Inc.

    Inventor： Jens Polney

    IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

    Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.

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