公开(公告)号：US20230012978A1

公开(公告)日：2023-01-19

申请号：US17946328

申请日：2022-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qisong LIN ,  Vamsi Pavan RAYAPROLU ,  Jiangang WU ,  Sampath K. RATNAM ,  Sivagnanam PARTHASARATHY ,  Shao Chun SHI

IPC: G06F11/07

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.

公开(公告)号：US20220157385A1

公开(公告)日：2022-05-19

申请号：US17589491

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan RAYAPROLU ,  Mustafa N. Kaynak ,  Michael Sheperek ,  Larry J. Koudele ,  Shane Nowell

IPC: G11C16/10 ,  G11C16/08 ,  G06F12/06

Abstract: One or more data units at a memory device and that are associated with one or more dice of a die group comprising a plurality of dice are programmed. A voltage offset bin associated with the plurality of dice in the die group is determined based on a subset of dice of the die group.

公开(公告)号：US20210096755A1

公开(公告)日：2021-04-01

申请号：US16666351

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Suresh RAJGOPAL ,  Ling WANG ,  Yue WEI ,  Vamsi Pavan RAYAPROLU

IPC: G06F3/06

Abstract: A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.

公开(公告)号：US20220068396A1

公开(公告)日：2022-03-03

申请号：US17008225

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan RAYAPROLU ,  Mustafa N. Kaynak ,  Michael Sheperek ,  Larry J. Koudele ,  Shane Nowell

IPC: G11C16/10 ,  G11C16/08 ,  G06F12/06

Abstract: One or more blocks at the memory device are programed. The one or more blocks are associated with a block family and with one or more dice of a die group. A voltage offset bin associated with the die group and the block family is determined based on a subset of dice of the die group. Metadata associated with the memory device is appended to include a record associating the die group and the block family with the voltage offset bin.