公开(公告)号：US20230012978A1

公开(公告)日：2023-01-19

申请号：US17946328

申请日：2022-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qisong LIN ,  Vamsi Pavan RAYAPROLU ,  Jiangang WU ,  Sampath K. RATNAM ,  Sivagnanam PARTHASARATHY ,  Shao Chun SHI

IPC: G06F11/07

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.

公开(公告)号：US20200210330A1

公开(公告)日：2020-07-02

申请号：US16234271

申请日：2018-12-27

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar MUCHHERLA ,  Sampath K. RATNAM ,  Ashutosh MALSHE ,  Peter Sean FEELEY

IPC: G06F12/02

Abstract: A processing device in a memory system determines whether a first data block of a plurality of data blocks on the memory component satisfies a first threshold criterion pertaining to a first number of the plurality of data blocks having a lower amount of valid data than a remainder of the plurality of data blocks. Responsive to the first data block satisfying the first threshold criterion, the processing device determines whether the first data block satisfies a second threshold criterion pertaining to a second number of the plurality of data blocks having been written to more recently than the remainder of the plurality of data blocks. Responsive to the first data block satisfying the second threshold criterion, the processing device determines whether a rate of change of an amount of valid data on the first data block satisfies a third threshold criterion. Responsive to the rate of change satisfying the third threshold criterion, the processing device identifies the first data block as a candidate for garbage collection on the memory component.

公开(公告)号：US20220383955A1

公开(公告)日：2022-12-01

申请号：US17883538

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar MUCHHERLA ,  Sampath K. RATNAM ,  Shane NOWELL ,  Sivagnanam PARTHASARATHY ,  Mustafa N. KAYNAK ,  Karl D. SCHUH ,  Peter FEELEY ,  Jiangang WU

IPC: G11C16/10 ,  G11C16/20 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26 ,  G11C16/34

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

公开(公告)号：US20220300415A1

公开(公告)日：2022-09-22

申请号：US17834794

申请日：2022-06-07

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar MUCHHERLA ,  Renato C. PADILLA ,  Sampath K. RATNAM ,  Saeed SHARIFI TEHRANI ,  Peter FEELEY ,  Kevin R. BRANDT

IPC: G06F12/02 ,  G06F12/121 ,  G06F3/06

Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.

公开(公告)号：US20190278655A1

公开(公告)日：2019-09-12

申请号：US15914402

申请日：2018-03-07

Applicant: Micron Technology, Inc.

Inventor： Larry J. KOUDELE ,  Mustafa N. KAYNAK ,  Michael SHEPEREK ,  Patrick R. KHAYAT ,  Sampath K. RATNAM

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.