公开(公告)号：US20180158610A1

公开(公告)日：2018-06-07

申请号：US15888351

申请日：2018-02-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： NORIYUKI INOUE ,  Takeo Arakawa ,  Kensuke Aoki ,  Hiromasa Saeki ,  Koichi Kanryo ,  Akihiro Tsuru ,  Haruhiko Mori

IPC: H01G4/06 ,  H01G4/30

Abstract: A capacitor that includes a conductive base material with high specific surface area, a dielectric layer covering the conductive base material with high specific surface area, and an upper electrode covering the dielectric layer, in which the conductive base material with high specific surface area is formed of a metal sintered body as a whole.

公开(公告)号：US20180114640A1

公开(公告)日：2018-04-26

申请号：US15849815

申请日：2017-12-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： NORIYUKI INOUE ,  Kazuo Hattori ,  Hiromasa Saeki

IPC: H01G4/08 ,  H01G4/248 ,  H01G4/33

CPC classification number: H01G4/08 ,  H01G4/248 ,  H01G4/33 ,  H01G9/012 ,  H01G9/0425 ,  H01G9/048 ,  H01G9/052 ,  H01G9/07 ,  H01G9/15 ,  H01L28/84

Abstract: A capacitor having an element main body including a metal high specific surface area substrate which has fine pores formed therein and has a large specific surface area; a dielectric layer in a prescribed region on the surface of the high specific surface area substrate including the inner surfaces of the pores; and a conductive part on the dielectric layer. A first terminal electrode is electrically connected to the high specific surface area substrate. A second terminal electrode is electrically connected to the conductive part. The element main body includes a first region that contributes to the acquisition of the capacitance and second regions having a smaller void ratio than the first region. The second regions have a void ratio of 25% or less.