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公开(公告)号：US09837897B2
公开(公告)日：2017-12-05
申请号：US15180238
申请日：2016-06-13
Applicant: NXP B.V.
Inventor： Jitendra Prabhakar Harshey , Ramesh Karpur , Pankaj Agrawal
CPC classification number: H02M3/157 , H02M1/08 , H02M3/158 , H02M2001/0006 , H02M2001/0009 , H02M2001/0032 , Y02B70/16
Abstract: A buck converter is described having a buck converter output for outputting an output supply voltage; a first power supply domain operably coupled to a power source; a second power supply domain; a power supply controller coupled to the first power supply domain, the second power supply domain and the buck converter output; wherein the power supply controller is configured to supply power to the second power supply domain from the first power supply domain or the buck converter output, in dependence of the buck converter output supply voltage. Changing the current supplied to the second power supply domain to the buck converter output may reduce the quiescent current consumption from a battery power source, prolonging battery life.
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公开(公告)号：US11038427B1
公开(公告)日：2021-06-15
申请号：US16734999
申请日：2020-01-06
Applicant: NXP B.V.
Inventor： Jitendra Prabhakar Harshey , Hendrik Johannes Bergveld , Edevaldo Pereira da Silva, Jr. , Koteswararao Nannapaneni , Uday Kumar Sajja
Abstract: A DC-DC converter operates in a burst mode having at least one charge cycle with a charging phase followed by a discharging phase. A charging phase is terminated when an inductor current flowing through an inductance connected to the DC-DC converter reaches a compensated peak-current threshold, wherein the compensated peak-current threshold compensates for charging-phase loop delay. A discharging phase is terminated when the inductor current reaches a compensated valley-current threshold, wherein the compensated valley-current threshold compensates for discharging-phase loop delay.
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公开(公告)号：US20220407503A1
公开(公告)日：2022-12-22
申请号：US17350855
申请日：2021-06-17
Applicant: NXP B.V.
Abstract: Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the first power source line; and a second AND gate with a first input and a second input connected to the inverse output of the first latch, wherein the first input is configured to receive a second power on reset signal based upon the second power source line, wherein the mode of the circuit is indicated by the outputs of the first latch and the second latch.
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Patent Agency Ranking
公开(公告)号：US20210211055A1
公开(公告)日：2021-07-08
申请号：US16734999
申请日：2020-01-06
Applicant: NXP B.V.
Inventor： Jitendra Prabhakar Harshey , Hendrik Johannes Bergveld , Edevaldo Pereira da Silva Junior , Koteswararao Nannapaneni , Uday Kumar Sajja
IPC: H02M3/158
Abstract: A DC-DC converter operates in a burst mode having at least one charge cycle with a charging phase followed by a discharging phase. A charging phase is terminated when an inductor current flowing through an inductance connected to the DC-DC converter reaches a compensated peak-current threshold, wherein the compensated peak-current threshold compensates for charging-phase loop delay. A discharging phase is terminated when the inductor current reaches a compensated valley-current threshold, wherein the compensated valley-current threshold compensates for discharging-phase loop delay.
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公开(公告)号：US10784783B1
公开(公告)日：2020-09-22
申请号：US16737623
申请日：2020-01-08
Applicant: NXP B.V.
Inventor： Jitendra Prabhakar Harshey , Hendrik Johannes Bergveld , Olivier Trescases , Edevaldo Pereira da Silva Junior , Stefano Pietri , Oscar Igor Robles Palacios
Abstract: A DC-DC converter selectively operates in at least a first burst mode having at least one first-mode charge cycle with a first-mode charging phase followed by a first-mode discharging phase or a second burst mode having at least one second-mode charge cycle with a second-mode charging phase followed by a second-mode discharging phase. A first-mode charging phase is terminated when an inductor current flowing through the inductance reaches a first-mode peak-current threshold, and a first-mode discharging phase is terminated when the inductor current reaches a first-mode valley-current threshold. A second-mode charging phase is terminated when the inductor current reaches a second-mode peak-current threshold, wherein the second-mode peak-current threshold is different from the first-mode peak-current threshold, and the second-mode discharging phase is terminated when the inductor current reaches a second-mode valley-current threshold, wherein the second-mode valley-current threshold is different from the first-mode valley-current threshold.
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公开(公告)号：US11539351B1
公开(公告)日：2022-12-27
申请号：US17350855
申请日：2021-06-17
Applicant: NXP B.V.
Abstract: Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the first power source line; and a second AND gate with a first input and a second input connected to the inverse output of the first latch, wherein the first input is configured to receive a second power on reset signal based upon the second power source line, wherein the mode of the circuit is indicated by the outputs of the first latch and the second latch.
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公开(公告)号：US10720838B1
公开(公告)日：2020-07-21
申请号：US16431927
申请日：2019-06-05
Applicant: NXP B.V.
Inventor： Jitendra Prabhakar Harshey , Olivier Trescases , Edevaldo Pereira Da Silva Junior , Stefano Pietri , Jurgen Geerlings , Hendrik Johannes Bergveld
Abstract: Embodiments provide forced-burst voltage regulation for burst mode direct-current-to-direct-current (DC-DC) converters in integrated circuits. The DC-DC converter generates an output voltage and operates in a burst mode to raise the output voltage to a threshold voltage. A controller is coupled to the DC-DC converter. In operation, the DC-DC converter is configured to perform the burst mode based upon a low-voltage detection for the output voltage. The DC-DC converter is further configured to perform the burst mode when a force-burst command is asserted by the controller to the DC-DC converter regardless of a state for the low-voltage detection. For one embodiment, the force-burst command is asserted as a burst control signal from the controller to the DC-DC converter to generate a long quiet period for sensitive actions. For another embodiment, the force-burst command is asserted using enable and refresh control signals to facilitate low-power operation.
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公开(公告)号：US20160380534A1
公开(公告)日：2016-12-29
申请号：US15180238
申请日：2016-06-13
Applicant: NXP B.V.
Inventor： Jitendra Prabhakar Harshey , Ramesh Karpur , Pankaj Agrawal
CPC classification number: H02M3/157 , H02M1/08 , H02M3/158 , H02M2001/0006 , H02M2001/0009 , H02M2001/0032 , Y02B70/16
Abstract: A buck converter is described having a buck converter output for outputting an output supply voltage; a first power supply domain operably coupled to a power source; a second power supply domain; a power supply controller coupled to the first power supply domain, the second power supply domain and the buck converter output; wherein the power supply controller is configured to supply power to the second power supply domain from the first power supply domain or the buck converter output, in dependence of the buck converter output supply voltage. Changing the current supplied to the second power supply domain to the buck converter output may reduce the quiescent current consumption from a battery power source, prolonging battery life.
Abstract translation: 描述具有用于输出输出电源电压的降压转换器输出的降压转换器; 可操作地耦合到电源的第一电源域; 第二电源领域; 耦合到第一电源域的电源控制器，第二电源域和降压转换器输出; 其中所述电源控制器被配置为根据所述降压转换器输出电源电压从所述第一电源域或所述降压转换器输出向所述第二电源域供电。 将提供给第二电源域的电流更改为降压转换器输出可能会降低电池电源的静态电流消耗，延长电池寿命。
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