公开(公告)号：US12278623B2

公开(公告)日：2025-04-15

申请号：US18332522

申请日：2023-06-09

Applicant: NXP B.V.

Inventor： Henricus Cornelis Johannes Büthker ,  Jyotirmoy Ghosh ,  Piotr Gibas ,  Edwin Schapendonk ,  Neha Goel ,  Namith Vishnu N

IPC: H03K17/22 ,  H03K3/037

Abstract: One example discloses a power on reset (POR) circuit, wherein a first circuit is configured to un-couple a power supply input from a resistor divider when the voltage on a second end of the capacitor is above a first circuit threshold; a second circuit configured to couple the second end of the capacitor to the power supply input when a voltage on at least one tap point of the resistor divider is above a second circuit threshold; wherein the comparator is coupled to at least one of the tap points, the reference potential, and a POR output; and wherein the comparator is configured to ramp-up a POR signal on the POR output when a voltage on the at least one of the tap points is greater than the comparator threshold.

公开(公告)号：US20240356543A1

公开(公告)日：2024-10-24

申请号：US18332522

申请日：2023-06-09

Applicant: NXP B.V.

Inventor： Henricus Cornelis Johannes Büthker ,  Jyotirmoy Ghosh ,  Piotr Gibas ,  Edwin Schapendonk ,  Neha Goel ,  Namith Vishnu N

IPC: H03K17/22 ,  H03K3/037

CPC classification number: H03K17/223 ,  H03K3/037

Abstract: One example discloses a power on reset (POR) circuit, wherein a first circuit is configured to un-couple a power supply input from a resistor divider when the voltage on a second end of the capacitor is above a first circuit threshold; a second circuit configured to couple the second end of the capacitor to the power supply input when a voltage on at least one tap point of the resistor divider is above a second circuit threshold; wherein the comparator is coupled to at least one of the tap points, the reference potential, and a POR output; and wherein the comparator is configured to ramp-up a POR signal on the POR output when a voltage on the at least one of the tap points is greater than the comparator threshold.

公开(公告)号：US20230417872A1

公开(公告)日：2023-12-28

申请号：US17846755

申请日：2022-06-22

Applicant: NXP B.V.

Inventor： Piotr Gibas ,  Tarik Saric

IPC: G01S7/40 ,  H03L7/099

CPC classification number: G01S7/4056 ,  H03L7/099 ,  G01S7/4004

Abstract: A radar system injects a calibrated current at a signal generator during a reset portion and acquisition portion of each chirp period. The signal generator employs “gear-switching” to reduce PLL bandwidth during an acquisition phase and to increase the phase lock loop (PLL) bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.

公开(公告)号：US11228318B1

公开(公告)日：2022-01-18

申请号：US17083968

申请日：2020-10-29

Applicant: NXP B.V.

Inventor： Tarik Saric ,  Piotr Gibas ,  Zhirui Zong

IPC: H03L7/107 ,  H03L7/093 ,  H03L7/099 ,  H03L7/089

Abstract: Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.