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公开(公告)号：US20240275365A1
公开(公告)日：2024-08-15
申请号：US18429939
申请日：2024-02-01
Applicant: NXP B.V.
Inventor： Gijsbert Willem Hardeman , Robert Rutten , Evert-Jan Daniel Pol , Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03H17/0294 , H03H17/0621 , H03H2017/0081
Abstract: A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.
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公开(公告)号：US11967967B2
公开(公告)日：2024-04-23
申请号：US17807454
申请日：2022-06-17
Applicant: NXP B.V.
Inventor： Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03M1/0604 , H03M1/0626 , H03M1/0687 , H03M1/502
Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.
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公开(公告)号：US20230412180A1
公开(公告)日：2023-12-21
申请号：US17807454
申请日：2022-06-17
Applicant: NXP B.V.
Inventor： Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03M1/0604 , H03M1/0687 , H03M1/0626 , H03M1/502
Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.
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