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公开(公告)号：US11522557B1
公开(公告)日：2022-12-06
申请号：US17388157
申请日：2021-07-29
Applicant: NXP B.V.
Inventor： Robert Rutten , Martin Kessel , Hendrik van der Ploeg , Lucien Johannes Breems , Muhammed Bolatkale , Evert-Jan Pol , Manfred Zupke , Bernard Burdiek , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
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公开(公告)号：US20170150521A1
公开(公告)日：2017-05-25
申请号：US15356451
申请日：2016-11-18
Applicant: NXP B.V.
Inventor： Jan Niehof , Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans
CPC classification number: H04W74/002 , H03M1/0678 , H03M1/08 , H03M1/123 , H03M1/183 , H04L5/0051
Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analogue-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
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公开(公告)号：US11716074B2
公开(公告)日：2023-08-01
申请号：US16455992
申请日：2019-06-28
Applicant: NXP B.V.
Inventor： Shagun Bajoria , Lucien Johannes Breems
IPC: H03K3/0233 , H03F3/45 , H03M3/00
CPC classification number: H03K3/0233 , H03F3/45264 , H03M3/43 , H03M3/464
Abstract: A high-speed comparator circuit is provided. The circuit includes an amplifier portion, a latch portion, and a negative capacitance portion. The amplifier portion includes an input coupled to receive an analog signal and an output. The latch portion is coupled to the amplifier portion. The latch portion is configured to provide at the output a digital value based on the analog signal. The negative capacitance portion is coupled to the output. The negative capacitance portion is configured to cancel parasitic capacitance coupled at the first output.
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公开(公告)号：US10541699B1
公开(公告)日：2020-01-21
申请号：US16157355
申请日：2018-10-11
Applicant: NXP B.V.
Inventor： Robert Rutten , Massimo Ciacci , Manfred Zupke , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans , Muhammed Bolatkale , Shagun Bajoria , Soheil Bahrami
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.
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公开(公告)号：US20240275365A1
公开(公告)日：2024-08-15
申请号：US18429939
申请日：2024-02-01
Applicant: NXP B.V.
Inventor： Gijsbert Willem Hardeman , Robert Rutten , Evert-Jan Daniel Pol , Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03H17/0294 , H03H17/0621 , H03H2017/0081
Abstract: A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240048146A1
公开(公告)日：2024-02-08
申请号：US18357689
申请日：2023-07-24
Applicant: NXP B.V.
Inventor： Shagun Bajoria , Muhammed Bolatkale , Lucien Johannes Breems , Robert Rutten , Mohammed Abo Alainein
IPC: H03M1/06
CPC classification number: H03M1/0602
Abstract: A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.
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公开(公告)号：US20230361781A1
公开(公告)日：2023-11-09
申请号：US18310184
申请日：2023-05-01
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems , Pierluigi Cenci , Shagun Bajoria , Mohammed Abo Alainein
Abstract: There is described an analog-to-digital converter, ADC, device (100), comprising:
i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13);
ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and
iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to:
swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).-
公开(公告)号：US11967967B2
公开(公告)日：2024-04-23
申请号：US17807454
申请日：2022-06-17
Applicant: NXP B.V.
Inventor： Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03M1/0604 , H03M1/0626 , H03M1/0687 , H03M1/502
Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.
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公开(公告)号：US20230412180A1
公开(公告)日：2023-12-21
申请号：US17807454
申请日：2022-06-17
Applicant: NXP B.V.
Inventor： Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03M1/0604 , H03M1/0687 , H03M1/0626 , H03M1/502
Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.
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公开(公告)号：US20170149388A1
公开(公告)日：2017-05-25
申请号：US15342009
申请日：2016-11-02
Applicant: NXP B.V.
Inventor： Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Breems , Johannes Brekelmans , Jan Niehof
CPC classification number: H03D7/12 , H03F1/3211 , H03F3/45183 , H03F3/45475 , H03F2200/331 , H03F2203/45138 , H03M3/422 , H03M3/454 , H03M3/476
Abstract: A summing node is provided for summing a first and second differential signals. Each of the first and second differential signals comprise respective direct and inverse signal components. The summing node comprises a first differential transistor pair comprising a first and second input and coupled to a first and second output. The summing node further comprises a second differential transistor pair comprising a third and fourth input and coupled to the first and second output. The first and fourth inputs are respectively coupled to the direct and inverse signal components of the first differential signal and the second and third inputs are respectively coupled to the direct and inverse signal components of the second differential signal.
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