公开(公告)号：US09570605B1

公开(公告)日：2017-02-14

申请号：US15150225

申请日：2016-05-09

Applicant: NXP B.V.

Inventor： Steven Thomas Peake

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66734

Abstract: A device is disclosed. The device includes a semiconductor substrate, a plurality of source lines formed on a surface of the semiconductor substrate. The plurality of source lines are laid in both X and Y directions. The device further includes a plurality of gate lines laid out over source lines in X direction in the plurality of source lines, a source contact line that connects source lines in the plurality of source lines that are terminating in Y direction, a gate contact line that connects the plurality of gate lines and a drain contact.

Abstract translation: 公开了一种设备。 该器件包括半导体衬底，形成在半导体衬底的表面上的多条源极线。 多个源极线被放置在X和Y方向上。 该装置还包括在多条源极线中沿X方向的源极线布置的多条栅极线，连接在Y方向终止的多条源极线中的源极线的源极接触线， 连接多个栅极线和漏极接触。

公开(公告)号：US20170077291A1

公开(公告)日：2017-03-16

申请号：US15233834

申请日：2016-08-10

Applicant: NXP B.V.

Inventor： Steven Thomas Peake ,  Philip Rutter ,  Chris Rogers

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/66734

Abstract: A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.

Abstract translation: 半导体器件和制造半导体器件的方法。 该器件包括具有第一导电类型的半导体衬底，位于衬底上的掺杂硅层，延伸到硅层中的沟槽以及位于沟槽中的栅电极和栅极电介质。 器件还包括漏极区域，具有位于沟槽附近并位于漏极区域之上的具有第二导电类型的体区域，以及具有位于沟槽附近并位于身体区域上方的具有第一导电类型的源极区域。 位于身体区域下方的区域中的掺杂硅层包括通过补偿在所述区域内形成净掺杂浓度的施主离子和受体离子。 作为深度的函数的掺杂硅层的净掺杂浓度在位于身体区域正下方的区域中具有最小值。

公开(公告)号：US20130146972A1

公开(公告)日：2013-06-13

申请号：US13682792

申请日：2012-11-21

Applicant: NXP B.V.

Inventor： Phil Rutter ,  Ian Culshaw ,  Steven Thomas Peake

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7817 ,  H01L29/7823

Abstract: A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes.

Abstract translation: 半导体使用隔离沟槽，并且提供了一个或多个附加的沟槽到需要隔离的沟槽。 这些额外的沟槽可以连接在晶体管栅极和漏极之间以提供额外的栅极 - 漏极电容，或者它们可以用于形成耦合到晶体管栅极的串联阻抗。 这些措施可以单独使用或组合使用，以降低开关速度，从而减少电流尖峰。

公开(公告)号：US20130146967A1

公开(公告)日：2013-06-13

申请号：US13659678

申请日：2012-10-24

Applicant: NXP B.V.

Inventor： Steven Thomas Peake ,  Phil Rutter

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734

Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Abstract translation: 具有侧面RESURF柱的沟槽栅极器件在栅极沟槽下方具有额外的注入。 附加的注入减少了RESURF柱之间的半导体漂移区域的有效宽度，并且这提供了额外的栅极屏蔽，其改善了器件的电特性。

公开(公告)号：US20150187913A1

公开(公告)日：2015-07-02

申请号：US14644272

申请日：2015-03-11

Applicant: NXP B.V.

Inventor： Steven Thomas Peake ,  Philip Rutter

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734

Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Abstract translation: 具有侧面RESURF柱的沟槽栅极器件在栅极沟槽下方具有额外的注入。 附加的注入减少了RESURF柱之间的半导体漂移区域的有效宽度，并且这提供了额外的栅极屏蔽，其改善了器件的电特性。

公开(公告)号：US09006822B2

公开(公告)日：2015-04-14

申请号：US13659678

申请日：2012-10-24

Applicant: NXP B.V.

Inventor： Steven Thomas Peake ,  Phil Rutter

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734

Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Abstract translation: 具有侧面RESURF柱的沟槽栅极器件在栅极沟槽下方具有额外的注入。 附加的注入减少了RESURF柱之间的半导体漂移区域的有效宽度，并且这提供了额外的栅极屏蔽，其改善了器件的电特性。