公开(公告)号：US20240234222A9

公开(公告)日：2024-07-11

申请号：US18048972

申请日：2022-10-24

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Zhiwei Gong ,  Neil Thomas Tracht

IPC: H01L23/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/041 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A method of forming a semiconductor device is provided. The method includes forming a first cavity at a first major surface of a first encapsulant. A first semiconductor die is affixed on the first major surface of the first encapsulant and a second semiconductor die is affixed on a bottom surface of the first cavity. A second encapsulant encapsulates the first semiconductor die, the second semiconductor die, and at least exposed portions of the first major surface of the first encapsulant. A package substrate is formed on a first major surface of the second encapsulant. The package substrate includes conductive traces interconnected to the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240136238A1

公开(公告)日：2024-04-25

申请号：US18048972

申请日：2022-10-23

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Zhiwei Gong ,  Neil Thomas Tracht

IPC: H01L23/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/041 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A method of forming a semiconductor device is provided. The method includes forming a first cavity at a first major surface of a first encapsulant. A first semiconductor die is affixed on the first major surface of the first encapsulant and a second semiconductor die is affixed on a bottom surface of the first cavity. A second encapsulant encapsulates the first semiconductor die, the second semiconductor die, and at least exposed portions of the first major surface of the first encapsulant. A package substrate is formed on a first major surface of the second encapsulant. The package substrate includes conductive traces interconnected to the first semiconductor die and the second semiconductor die.

公开(公告)号：US20210050317A1

公开(公告)日：2021-02-18

申请号：US16540342

申请日：2019-08-14

Applicant: NXP B.V.

Inventor： Paul Southworth ,  Zhiwei Gong

IPC: H01L23/00 ,  H01L23/532 ,  H01L21/768

Abstract: Embodiments are provided for package semiconductor devices, each device including: a low stress pad structure comprising: a dielectric layer, a seed layer having: a center section, and a ring section formed around the center section and over a top surface of the dielectric layer, wherein the ring section of the seed layer includes a set of elongated openings through which a portion of the top surface of the dielectric layer is exposed, and a metal layer having: an inner section formed over a top surface of the center section of the seed layer, and an outer section formed over a top surface of the ring section of the seed layer, wherein a bottom surface of the outer section of the metal layer directly contacts the portion of the top surface of the dielectric layer exposed through the set of elongated openings.

公开(公告)号：US20240347928A1

公开(公告)日：2024-10-17

申请号：US18600833

申请日：2024-03-11

Applicant: NXP B.V.

Inventor： Mustafa Acar ,  Zhiwei Gong ,  Robert Joseph Wenzel ,  Tingdong Zhou

IPC: H01Q21/06 ,  H01Q9/04 ,  H01Q21/00

CPC classification number: H01Q21/065 ,  H01Q9/0414 ,  H01Q21/0087

Abstract: An antenna package and method of manufacturing an antenna package is disclosed. The antenna package includes a first substrate and second substrate in a stacked arrangement. A first plurality of patch antennas and a plurality of decoupling capacitors is arranged on a first major surface of the first substrate. One or more decoupling capacitor of the plurality of decoupling capacitors is located between adjacent patch antennas of the first plurality of patch antennas. The second substrate includes a second plurality of patch antennas. One or more decoupling capacitors of the plurality of decoupling capacitors includes a first terminal configured to be in contact with the first substrate and a second terminal configured to be in contact with the first substrate and the second substrate.

公开(公告)号：US10937750B1

公开(公告)日：2021-03-02

申请号：US16540342

申请日：2019-08-14

Applicant: NXP B.V.

Inventor： Paul Southworth ,  Zhiwei Gong

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments are provided for package semiconductor devices, each device including: a low stress pad structure comprising: a dielectric layer, a seed layer having: a center section, and a ring section formed around the center section and over a top surface of the dielectric layer, wherein the ring section of the seed layer includes a set of elongated openings through which a portion of the top surface of the dielectric layer is exposed, and a metal layer having: an inner section formed over a top surface of the center section of the seed layer, and an outer section formed over a top surface of the ring section of the seed layer, wherein a bottom surface of the outer section of the metal layer directly contacts the portion of the top surface of the dielectric layer exposed through the set of elongated openings.