公开(公告)号：US20070008907A1

公开(公告)日：2007-01-11

申请号：US11360661

申请日：2006-02-24

申请人： Naoki Odate ,  Katsuhiro Yoda ,  Seiichi Nishijima ,  Kazuhiko Shoji

发明人： Naoki Odate ,  Katsuhiro Yoda ,  Seiichi Nishijima ,  Kazuhiko Shoji

IPC分类号： H04L12/28

CPC分类号： G06F15/7867

摘要： A reconfigurable LSI which can actualize a plurality of functions by reconfiguration based on configuration information, comprises at least a plurality of arithmetic processing modules, has state information for indicating the transition of the function from a previous state to a next state, transition condition information for indicating the condition for transitioning from the previous state to the next state, and output information for switching the connection between the arithmetic processing module corresponding to the transition condition and the data network connected to the arithmetic processing module, and has a reconfiguration control circuit which transmits the output information corresponding to the next state to a selector for switching between the arithmetic processing module and the data network when the conditions for transition are received from the arithmetic processing module and matches the condition of the transition condition information.

摘要翻译： 可以通过基于配置信息的重构来实现多个功能的可重构LSI包括至少多个算术处理模块，具有用于指示功能从先前状态到下一状态的转换的状态信息，用于 指示从先前状态转换到下一状态的条件，以及用于切换与转换条件相对应的运算处理模块与连接到算术处理模块的数据网络之间的连接的输出信息，并且具有发送 当从算术处理模块接收到转换条件并与转换条件信息的条件匹配时，将与下一状态相对应的输出信息提供给选择器，用于在算术处理模块和数据网络之间进行切换。

公开(公告)号：US07394755B2

公开(公告)日：2008-07-01

申请号：US10859534

申请日：2004-06-03

申请人： Seiichi Nishijima ,  Katsuhiro Yoda ,  Daisuke Fujita

发明人： Seiichi Nishijima ,  Katsuhiro Yoda ,  Daisuke Fujita

IPC分类号： H04J13/00

CPC分类号： H04N21/43615 ,  H03M13/235 ,  H03M13/4107 ,  H04N21/4135 ,  H04N21/43637

摘要： A semi-fixed circuit has a plurality of flip flops connectable in series, a first selector and a second selector, and is capable of operations of a plurality of kinds of scrambler and the like. The first selector selects any one of an exclusive OR signal of an input signal and a first feedback signal, the first feedback signal and the input signal, and outputting the result to a first flip flop. The second selector is capable of selecting an exclusive OR signal of an output signal of a second flip flop and a second feedback signal, an output signal of the second flip flop and the second feedback signal, and outputting the result to the first selector as the first feedback signal.

摘要翻译： 半固定电路具有可串联连接的多个触发器，第一选择器和第二选择器，并且能够操作多种扰频器等。 第一选择器选择输入信号和第一反馈信号的异或信号，第一反馈信号和输入信号中的任何一个，并将结果输出到第一触发器。 第二选择器能够选择第二触发器和第二反馈信号的输出信号的异或信号，第二触发器的输出信号和第二反馈信号，并将结果输出到第一选择器作为 第一反馈信号。

公开(公告)号：US20050094804A1

公开(公告)日：2005-05-05

申请号：US10859534

申请日：2004-06-03

申请人： Seiichi Nishijima ,  Katsuhiro Yoda ,  Daisuke Fujita

发明人： Seiichi Nishijima ,  Katsuhiro Yoda ,  Daisuke Fujita

IPC分类号： H03K3/84 ,  H03M13/09 ,  H03M13/41 ,  H04K1/00 ,  H04L1/00

CPC分类号： H04N21/43615 ,  H03M13/235 ,  H03M13/4107 ,  H04N21/4135 ,  H04N21/43637

摘要： A semi-fixed circuit has a plurality of flip flops connectable in series, a first selector and a second selector, and is capable of operations of a plurality of kinds of scrambler and the like. The first selector selects any one of an exclusive OR signal of an input signal and a first feedback signal, the first feedback signal and the input signal, and outputting the result to a first flip flop. The second selector is capable of selecting an exclusive OR signal of an output signal of a second flip flop and a second feedback signal, an output signal of the second flip flop and the second feedback signal, and outputting the result to the first selector as the first feedback signal.

摘要翻译： 半固定电路具有可串联连接的多个触发器，第一选择器和第二选择器，并且能够操作多种扰频器等。 第一选择器选择输入信号和第一反馈信号的异或信号，第一反馈信号和输入信号中的任何一个，并将结果输出到第一触发器。 第二选择器能够选择第二触发器和第二反馈信号的输出信号的异或信号，第二触发器的输出信号和第二反馈信号，并将结果输出到第一选择器作为 第一反馈信号。

公开(公告)号：US20070190994A1

公开(公告)日：2007-08-16

申请号：US11439981

申请日：2006-05-25

申请人： Yuki Sakai ,  Seiichi Nishijima ,  Naoki Oodate

发明人： Yuki Sakai ,  Seiichi Nishijima ,  Naoki Oodate

IPC分类号： H04M3/00

CPC分类号： H04B1/406 ,  H04B1/0003

摘要： Reconfigurable units each include a hardware circuit having one part of a radio procedure function and a reconfigurable circuit having another part of the radio procedure function. An extension interface unit includes a switch circuit having a changeable connection specification to interconnect the reconfigurable units. A memory unit stores logic information for changing logics of the reconfigurable circuits and the connection specification of the switch circuit. A control unit downloads into the memory unit the logic information supplied from outside of the software defined radio. Rewriting the logics of the reconfigurable circuits according to the logic information and switching connection information of the switch circuit makes it possible to realize an optimum logic circuit in compliance with a radio communication to be used. In other words, it is possible to improve the scalability of the radio procedure function of the software defined radio.

摘要翻译： 可重构单元各自包括具有无线电过程功能的一部分的硬件电路和具有无线电过程功能的另一部分的可重新配置电路。 扩展接口单元包括具有可互换连接规范以互连可重配置单元的开关电路。 存储单元存储用于改变可重构电路的逻辑和开关电路的连接规范的逻辑信息。 控制单元从软件定义的无线电的外部向存储器单元下载逻辑信息。 根据开关电路的逻辑信息和切换连接信息重写可重构电路的逻辑，使得可以实现符合要使用的无线电通信的最佳逻辑电路。 换句话说，可以提高软件定义无线电的无线电程序功能的可扩展性。

公开(公告)号：US07756224B2

公开(公告)日：2010-07-13

申请号：US11544625

申请日：2006-10-10

申请人： Seiichi Nishijima

发明人： Seiichi Nishijima

IPC分类号： H04L27/06

CPC分类号： H03M13/6516 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6519

摘要： A setting register is provided in which parameters including a code rate, a constraint length, and a generator polynomial are changeably set according to a type of wireless communication standard, the parameters. A branch metric calculating unit generates branch metric information in an amount according to the code rate. A replica generating unit replicates, based on the generator polynomial, a specification of an encoder at a transmitting-end, and generates setting information related to selection of the branch metric information. A branch metric selection unit performs selection of an upper branch metric and a lower branch metric from among a plurality of pieces of the branch metric information, based on the setting information. An ACS unit determines a path metric for each step in a trellis diagram based on the upper branch metric and the lower branch metric, and to determine a surviving branch and a path metric value.

摘要翻译： 提供了一种设置寄存器，其中包括码率，约束长度和生成多项式的参数根据无线通信标准的类型而变化地设置。 分支度量计算单元根据码率生成分支量度信息。 复制生成单元基于生成多项式复制发送端的编码器的规格，生成与分支度量信息的选择有关的设定信息。 分支度量选择单元基于设置信息，从多条分支度量信息中选择上分支度量和下分支度量。 ACS单元基于上分支度量和下分支度量来确定网格图中每个步骤的路径度量，并确定幸存分支和路径度量值。

公开(公告)号：US20070183539A1

公开(公告)日：2007-08-09

申请号：US11544625

申请日：2006-10-10

申请人： Seiichi Nishijima

发明人： Seiichi Nishijima

IPC分类号： H03D1/00 ,  H03M13/03

CPC分类号： H03M13/6516 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6519

摘要： A setting register is provided in which parameters including a code rate, a constraint length, and a generator polynomial are changeably set according to a type of wireless communication standard, the parameters. A branch metric calculating unit generates branch metric information in an amount according to the code rate. A replica generating unit replicates, based on the generator polynomial, a specification of an encoder at a transmitting-end, and generates setting information related to selection of the branch metric information. A branch metric selection unit performs selection of an upper branch metric and a lower branch metric from among a plurality of pieces of the branch metric information, based on the setting information. An ACS unit determines a path metric for each step in a trellis diagram based on the upper branch metric and the lower branch metric, and to determine a surviving branch and a path metric value.

摘要翻译： 提供了一种设置寄存器，其中包括码率，约束长度和生成多项式的参数根据无线通信标准的类型而变化地设置。 分支度量计算单元根据码率生成分支量度信息。 复制生成单元基于生成多项式复制发送端的编码器的规格，生成与分支度量信息的选择有关的设定信息。 分支度量选择单元基于设置信息，从多条分支度量信息中选择上分支度量和下分支度量。 ACS单元基于上分支度量和下分支度量来确定网格图中每个步骤的路径度量，并确定幸存分支和路径度量值。

公开(公告)号：US07664526B2

公开(公告)日：2010-02-16

申请号：US11443150

申请日：2006-05-31

申请人： Yuki Sakai ,  Seiichi Nishijima ,  Naoki Oodate

发明人： Yuki Sakai ,  Seiichi Nishijima ,  Naoki Oodate

IPC分类号： H04B1/38 ,  H04M1/00

CPC分类号： H04L5/1438

摘要： A radio device from which communication is started transmits a confirmation signal to a counterpart, and if an acknowledgement signal is not returned from the counterpart, switches a communication mode to another communication mode. This operation is repeated until the acknowledgement signal is returned from the counterpart. Thus, the communication mode is matched with that of the counterpart, thereby establishing a communication link with the counterpart. A radio device caused to start communication by a second radio device receives a signal from the second radio device. The radio device switches a communication mode to another communication mode if synchronization is failed to be established. This operation is repeated until the synchronization is succeeded to be established. Thus, the communication mode is matched with that of the second radio device to be a communication counterpart, thereby establishing a link with the second radio device.

摘要翻译： 从其开始通信的无线电装置向对方发送确认信号，并且如果不从对方返回确认信号，则将通信模式切换到另一通信模式。 重复该操作，直到确认信号从对方返回。 因此，通信模式与对方的通信模式相匹配，从而建立与对方的通信链路。 由第二无线电设备开始通信的无线电设备从第二无线电设备接收信号。 如果无法建立同步，无线电设备将通信模式切换到另一通信模式。 重复该操作，直到同步成功建立。 因此，通信模式与作为通信对方的第二无线电设备的通信模式相匹配，从而建立与第二无线电设备的链路。

公开(公告)号：US20060202715A1

公开(公告)日：2006-09-14

申请号：US11244043

申请日：2005-10-06

申请人： Seiichi Nishijima

发明人： Seiichi Nishijima

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3897 ,  G06F15/7867 ,  H03K19/17728 ,  H03K19/17792

摘要： The present invention is a re-configurable circuit capable of reducing latency by selecting a route for skipping the FF of an operation unit and outputting data to a connection destination operation unit if an accumulated process time is below an operation cycle allocated to the operation unit. The operation unit comprises at least a selector, a flip-flop and an operator. In a program for generating configuration information for switching the configuration of the operation unit of the re-configurable circuit, the selector selects the use/non-use of the flip-flop, based on the configuration information and selector switching condition is reflected in the configuration information for determining whether to take a route for transferring data inputted to the selector to the operator or a route for transferring the data to the operator skipping the flip-flop.

摘要翻译： 本发明是一种可再配置电路，其能够通过选择用于跳过操作单元的FF的路由来减少等待时间，并且如果累积处理时间低于分配给操作单元的操作周期，则向连接目的地操作单元输出数据。 操作单元至少包括选择器，触发器和操作器。 在用于产生用于切换可重配置电路的操作单元的配置的配置信息的程序中，选择器基于配置信息选择触发器的使用/不使用，并且选择器切换条件反映在 用于确定是否将用于将输入到选择器的数据传送到操作者的路由的配置信息或用于将数据传送到跳过触发器的操作者的路由。

公开(公告)号：US06482514B1

公开(公告)日：2002-11-19

申请号：US09827340

申请日：2001-04-06

申请人： Mitsugu Matsumoto ,  Akira Shimizu ,  Seiichi Nishijima

发明人： Mitsugu Matsumoto ,  Akira Shimizu ,  Seiichi Nishijima

IPC分类号： D01F5602

CPC分类号： D01F1/10 ,  D01F2/06 ,  Y10T428/2913 ,  Y10T428/2927 ,  Y10T428/2965

摘要： The invention provides deodorant rayon fibers having a superior deodorization performance. The deodorant rayon fibers are produced by implanting a large quantity of fine grains produced by milling white charcoal in a matrix of the rayon fiber. After adding and mixing a water dispersion which disperses the large quantity of fine grains into viscose solutin, and then spinning, thereby the deodorant rayon fibers are produced. The fine grains obtained by milling the white charcoal do not form spheres with smooth surfaces, but their configurations are irregular with projections. As a result, even when they are implanted in the matrix of the rayon fiber, the projections tend to be exposed on the surfaces of the rayon fibers. The exposed fine grains adsorb odor gases into themselves, thereby their superior deodoization performance is performed.

摘要翻译： 本发明提供具有优异除臭性能的除臭人造丝纤维。 除臭人造丝纤维通过在人造丝纤维的基质中植入大量由白色木炭制成的细晶粒来制造。 加入并混合将大量细粒分散到粘胶溶液中的水分散体，然后纺丝，从而制得除臭人造纤维。 通过研磨白炭获得的细晶粒不会形成具有光滑表面的球体，但是它们的构型不规则。 结果，即使将它们植入人造丝纤维的基质中，也会使人造丝纤维的表面露出。 暴露的细颗粒将气味吸附到自身中，从而实现其优异的除臭性能。

公开(公告)号：US07315933B2

公开(公告)日：2008-01-01

申请号：US11244043

申请日：2005-10-06

申请人： Seiichi Nishijima

发明人： Seiichi Nishijima

IPC分类号： G06F15/00

CPC分类号： H03K19/17736 ,  G06F9/3875 ,  G06F9/3885 ,  G06F9/3897 ,  G06F15/7867 ,  H03K19/17728 ,  H03K19/17792

摘要： The present invention is a re-configurable circuit capable of reducing latency by selecting a route for skipping the FF of an operation unit and outputting data to a connection destination operation unit if an accumulated process time is below an operation cycle allocated to the operation unit.The operation unit comprises at least a selector, a flip-flop and an operator. In a program for generating configuration information for switching the configuration of the operation unit of the re-configurable circuit, the selector selects the use/non-use of the flip-flop, based on the configuration information and selector switching condition is reflected in the configuration information for determining whether to take a route for transferring data inputted to the selector to the operator or a route for transferring the data to the operator skipping the flip-flop.

摘要翻译： 本发明是一种可再配置电路，其能够通过选择用于跳过操作单元的FF的路由来减少等待时间，并且如果累积处理时间低于分配给操作单元的操作周期，则向连接目的地操作单元输出数据。 操作单元至少包括选择器，触发器和操作器。 在用于产生用于切换可重配置电路的操作单元的配置的配置信息的程序中，选择器基于配置信息选择触发器的使用/不使用，并且选择器切换条件反映在 用于确定是否将用于将输入到选择器的数据传送到操作者的路由的配置信息或用于将数据传送到跳过触发器的操作者的路由。