Abstract:
An improved branch-and-bound process of interval arithmetic subdivision in furtherance of computation of rigorous error bounds on integrated digital scene information for two dimensional display is provided. More particularly, a first aspect of the subject process includes pseudo-randomly subdividing an interval domain comprising a set of interval variables in furtherance of ascertaining a characteristic contribution of the interval variables of said set of interval variables to an image space comprising at least a sub-pixel area. A further aspect, either alone or in combination with the first aspect contemplates pseudo-randomly discarding a select partitioning of interval variables of a set of interval variables of a geometric function from a computed solution of an interval arithmetic branch-and-bound process.
Abstract:
A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.
Abstract:
A computer executable method of processing a representation of a modal interval polynomial is provided. A representation of a modal interval polynomial is generally provided as input, more particularly, a representation comprising a modal interval function variable and an array of modal interval coefficients. Each modal interval linear interpolation of each of the modal interval coefficients of the array are recursively processed until a single modal interval coefficient remains in the array. For each iteration of the recursive processing, a modal interval linear interpolation operation is executed.
Abstract:
A computer executable method of processing a representation of a modal interval spherical projection is provided. A representation of a vector comprised of modal intervals X, Y, and Z is provided wherein each modal interval of the modal intervals are delimited by first and second marks of a digital scale. An analytical expression of an azimuthal spherical projection is partitioned into terms of a pair of independent functions wherein a function of the pair exhibits a monotonicity over piecewise domains of the function. A modal interval analysis is performed upon the function wherein arguments of said piecewise domains are modal intervals.
Abstract:
A computer executable method of performing a modal interval operation, and system for performing same is provided. The method includes providing representations of first and second modal interval operands. Each modal interval operand of the operands is delimited by first and second marks of a digital scale, each mark of the marks comprises a bit-pattern. Each bit-pattern of the bit-patterns of the marks of each of the modal interval operands are examined, and conditions of a set of status flags corresponding to each bit-pattern of the bit-patterns of the marks are set. A bit-mask is computed wherein the mask is based upon the set condition of the status flag sets and a presence/absence of an exceptional arithmetic condition, and a presence/absence of an indefinite operand are each represented by a bit of said bits of said bit mask.
Abstract:
A modal interval representation having improved computational utility is provided. The modal interval representation generally includes a binary quantifier, and a set theoretical interval for select permutations of marks of a pair of marks of an IEEE standard 754 digital scale. The set theoretical interval includes combinations of real numbers, infinities, signed zeros, and pseudo-numbers, with select permutations of the marks comprising bounded, unbounded, pointwise and indefinite modal intervals.
Abstract:
A computer executable method of performing a modal interval operation, and system for performing same is provided. The method includes providing representations of first and second modal interval operands. Each modal interval operand of the operands is delimited by first and second marks of a digital scale, each mark of the marks comprises a bit-pattern. Each bit-pattern of the bit-patterns of the marks of each of the modal interval operands are examined, and conditions of a set of status flags corresponding to each bit-pattern of the bit-patterns of the marks are set. A bit-mask is computed wherein the mask is based upon the set condition of the status flag sets and a presence/absence of an exceptional arithmetic condition, and a presence/absence of an indefinite operand are each represented by a bit of said bits of said bit mask.
Abstract:
A computer executable method of performing a modal interval operation, and system for performing same is provided. The method includes providing representations of first and second modal interval operands. Each modal interval operand of the operands is delimited by first and second marks of a digital scale, each mark of the marks comprises a bit-pattern. Each bit-pattern of the bit-patterns of the marks of each of the modal interval operands are examined, and conditions of a set of status flags corresponding to each bit-pattern of the bit-patterns of the marks are set. A bit-mask is computed wherein the mask is based upon the set condition of the status flag sets and a presence/absence of an exceptional arithmetic condition, and a presence/absence of an indefinite operand are each represented by a bit of said bits of said bit mask.
Abstract:
A single-pass, order-independent method in support of rendering transparency effects into a computer generated image is provided. A geometric primitive of a scene is rasterized so as to convert the geometric primitive into a set of pixels. For at least each pixel or subpixel, a stipple pattern is selected from a set of unique stipple patterns. The set of unique stipple patterns is characterized by a select opacity value with the stipple pattern delimiting a unique set of pixels in the computer generated image which contributes to a visible surface determination.
Abstract:
A logic circuit computes various modal interval (MI) arithmetic values using a plurality of arithmetic function units (AFUs), each dedicated to compute a specific MI arithmetic operation. The AFUs receive first and second MI operand values each encoded in first and second operand signals. Each AFU provides a MI result value encoded in a result signal to a multiplexer. The multiplexer receives a selector signal specifying the MI arithmetic operation desired, and provides to a result register, an output signal encoding the MI result value specified by the selector signal. The result register stores the MI result value.