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    Reduced floating-point precision arithmetic circuitry
    1.
    发明授权
    Reduced floating-point precision arithmetic circuitry 有权

    公开(公告)号：US10073676B2

    公开(公告)日：2018-09-11

    申请号：US15272231

    申请日：2016-09-21

    Applicant: Altera Corporation

    Inventor： Martin Langhammer

    IPC: G06F7/487 ,  G06F17/16

    CPC classification number: G06F7/485 ,  G06F7/4876 ,  G06F7/49957 ,  G06F7/5443 ,  G06F9/30014 ,  G06F17/16 ,  G06F2207/382 ,  G06F2207/483

    Abstract: The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial product of first and second input signals, while a second partial product generator may generate a second partial product of third and fourth input signals. A compressor circuit may generate carry and sum vector signals based on the first and second partial products; and circuitry may anticipate rounding and normalization operations by generating in parallel based on the carry and sum vector signals at least two results when performing the single-precision floating-point operation and at least four results when performing the two half-precision floating-point operations.

    Floating point addition with early shifting
    2.
    发明授权
    Floating point addition with early shifting 有权

    公开(公告)号：US10061561B2

    公开(公告)日：2018-08-28

    申请号：US15258051

    申请日：2016-09-07

    Applicant: ARM Limited

    Inventor： David Raymond Lutz

    IPC: G06F7/485 ,  G06F5/01

    CPC classification number: G06F7/485 ,  G06F5/01 ,  G06F2205/00 ,  G06F2207/483

    Abstract: A floating point adder includes leading zero anticipation circuitry to determine a number of leading zeros within a result significand value of a sum of a first floating point operand and a second floating point operand. This number of leading zeros is used to generate a mask which in turn selects input bits from a non-normalized significand produced by adding the first significand value and the second significand value. The non-normalized significand is then normalized at the same time as the output rounding bits used to round the normalized significand value are generated by rounding bit generation circuitry.

    ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE
    4.
    发明申请
    ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE 审中-公开
    算术处理装置和控制算术处理装置的方法

    公开(公告)号：US20170017466A1

    公开(公告)日：2017-01-19

    申请号：US15204304

    申请日：2016-07-07

    Applicant: FUJITSU LIMITED

    Inventor： Mikio Hondo

    IPC: G06F7/483

    CPC classification number: G06F7/4833 ,  G06F7/556 ,  G06F2207/483

    Abstract: An arithmetic processing device includes: a first memory configured to store values of a first coefficient of a logarithmic function, where the logarithmic function is decomposed into a series operation term and the coefficient term, depending on respective values of a first bit group included in operand data of a first instruction to calculate the value of the first coefficient; a second memory configured to store values of a second coefficient included in the series operation term depending on the respective values of the first bit group included in operand data of a second instruction to calculate the value of the second coefficient; and a selector configured to select the value of the first coefficient read from the first memory based on the execution of the first instruction and select the value of the second coefficient read from the second memory based on the execution of the second instruction.

    Abstract translation: 算术处理装置包括：第一存储器，被配置为存储对数函数的第一系数的值，其中对数函数被分解为串联运算项和系数项，这取决于包括在操作数中的第一位组的相应值 用于计算第一系数的值的第一指令的数据; 第二存储器，被配置为根据包括在第二指令的操作数数据中的第一位组的各个值来存储包括在串联运算项中的第二系数的值，以计算第二系数的值; 以及选择器，被配置为基于第一指令的执行来选择从第一存储器读取的第一系数的值，并且基于第二指令的执行来选择从第二存储器读取的第二系数的值。

    FLOATING-POINT ADDER CIRCUITRY
    8.
    发明申请
    FLOATING-POINT ADDER CIRCUITRY 有权
    浮点补偿电路

    公开(公告)号：US20150067010A1

    公开(公告)日：2015-03-05

    申请号：US14019196

    申请日：2013-09-05

    Applicant: Altera Corporation

    Inventor： Tomasz Czajkowski

    IPC: G06F17/10

    CPC classification number: G06F7/485 ,  G06F5/012 ,  G06F7/49915 ,  G06F17/10 ,  G06F2207/483

    Abstract: An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.

    Abstract translation: 提供一种集成电路，其执行涉及至少三个浮点数的浮点加法或减法运算。 通过动态扩展尾数位数，以最大指数确定浮点数，将其他浮点数的尾数向右移动，对浮点数进行预处理。 每个扩展尾数具有进入浮点运算的尾数的位数的至少两倍。 精确的位扩展取决于要添加的浮点数的数量。 指数小于最大指数的所有浮点数的尾数向右移动。 右移位的数量取决于最大指数和相应浮点指数之间的差异。

    PROCESSOR AND CONTROL METHOD OF PROCESSOR
    9.
    发明申请
    PROCESSOR AND CONTROL METHOD OF PROCESSOR 有权
    处理器的处理器和控制方法

    公开(公告)号：US20140379772A1

    公开(公告)日：2014-12-25

    申请号：US14479392

    申请日：2014-09-08

    Applicant: FUJITSU LIMITED

    Inventor： Mikio Hondo

    IPC: G06F7/556 ,  G06F7/483

    CPC classification number: G06F7/556 ,  G06F7/483 ,  G06F2207/483 ,  G06F2207/556

    Abstract: A processor includes: an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation; a storage unit that stores a mantissa part of the coefficient; a constant generating unit that reads constant data corresponding to a second part of the input data from the storage unit; and a selecting unit that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.

    Abstract translation: 处理器包括：指数生成单元，其基于接收到的输入数据的第一部分生成由浮点数格式表示的系数的指数部分，将指数函数分解为串联运算时获得的系数，并且系数 用于系列操作; 存储单元，其存储所述系数的尾数部分; 常数生成单元，其从所述存储单元读取与所述输入数据的第二部分相对应的恒定数据; 以及选择单元，当要执行的指令是用于计算指数函数的系数的系数计算指令时，从常数生成单元选择并输出常数数据。

    Modal interval processor
    10.
    发明授权
    Modal interval processor 有权
    模态间隔处理器

    公开(公告)号：US08849881B2

    公开(公告)日：2014-09-30

    申请号：US13114672

    申请日：2011-05-24

    Applicant: Nathan T. Hayes

    Inventor： Nathan T. Hayes

    IPC: G06F7/00 ,  G06F7/499

    CPC classification number: G06F7/485 ,  G06F7/49989 ,  G06F2207/483

    Abstract: A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.

    Abstract translation: 逻辑电路使用多个算术功能单元来计算各种模态间隔算术值。 多路复用器将期望的算术值门控到存储寄存器。

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