公开(公告)号：US20150278053A1

公开(公告)日：2015-10-01

申请号：US14675271

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Connie Wai Mun Cheung

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for managing a failed memory module, including: receiving a first request to access a first memory address; identifying a memory module identifier (ID) from an end bit segment of the first memory address in the first request; generating, based on the memory module ID matching the failed memory module, a first revised memory address from the first memory address; and sending the first request with the first revised memory address to a memory controller for interpretation.

Abstract translation: 一种用于管理故障存储器模块的方法，包括：接收访问第一存储器地址的第一请求; 从所述第一请求中的所述第一存储器地址的结束位段识别存储器模块标识符（ID）; 基于与所述故障存储器模块匹配的存储器模块ID，从所述第一存储器地址生成第一修改的存储器地址; 并且将具有第一修改的存储器地址的第一请求发送到用于解释的存储器控​​制器。

公开(公告)号：US20140281237A1

公开(公告)日：2014-09-18

申请号：US13830967

申请日：2013-03-14

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Paul N. Loewenstein ,  Stephen E. Phillips ,  David Richard Smentek ,  Connie Wai Mun Cheung ,  Serena Wing Yee Leung ,  Damien Walker ,  Ramaswamy Sivaramakrishnan

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828

Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.

Abstract translation: 一种用于高速缓存一致性的方法，包括：通过部分有序请求网络（RN）的请求者缓存（RC）广播对多个从高速缓存的高速缓存线的对等（P2P）请求; 当P2P请求正在等待时，由RC接收和通过RN接收来自网关的高速缓存行的转发请求; 由所述RC接收所述转发请求后，从所述多个从属高速缓存中接收对所述P2P请求的多个响应; 在所述RC中设置所述高速缓存行的处理器内状态，其中所述处理器内状态还指定所述高速缓存行的处理器间状态; 以及在设置处理器内状态之后，在P2P请求完成之后，由RC发出对转发请求的响应; 以及响应于发出对所转发的请求的响应，由RC修改处理器内状态。

公开(公告)号：US08972663B2

公开(公告)日：2015-03-03

申请号：US13830967

申请日：2013-03-14

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Stephen E. Phillips ,  David Richard Smentek ,  Connie Wai Mun Cheung ,  Serena Wing Yee Leung ,  Damien Walker ,  Ramaswamy Sivaramakrishnan

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828

Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.

Abstract translation: 一种用于高速缓存一致性的方法，包括：通过部分有序请求网络（RN）的请求者缓存（RC）广播对多个从高速缓存的高速缓存线的对等（P2P）请求; 当P2P请求正在等待时，由RC接收和通过RN接收来自网关的高速缓存行的转发请求; 由所述RC接收所述转发请求后，从所述多个从属高速缓存中接收对所述P2P请求的多个响应; 在所述RC中设置所述高速缓存行的处理器内状态，其中所述处理器内状态还指定所述高速缓存行的处理器间状态; 以及在设置处理器内状态之后，在P2P请求完成之后，由RC发出对转发请求的响应; 以及响应于发出对所转发的请求的响应，由RC修改处理器内状态。

公开(公告)号：US09645903B2

公开(公告)日：2017-05-09

申请号：US14675271

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Connie Wai Mun Cheung

IPC: G06F11/00 ,  G06F11/20 ,  G06F12/1036 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for managing a failed memory module, including: receiving a first request to access a first memory address; identifying a memory module identifier (ID) from an end bit segment of the first memory address in the first request; generating, based on the memory module ID matching the failed memory module, a first revised memory address from the first memory address; and sending the first request with the first revised memory address to a memory controller for interpretation.

公开(公告)号：US09569322B2

公开(公告)日：2017-02-14

申请号：US14675376

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Connie Wai Mun Cheung

IPC: G06F12/00 ,  G06F11/20 ,  G06F12/10 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.

Abstract translation: 一种用于寻址方案之间的存储器迁移的方法，包括：接收访问第一存储器地址的第一请求和访问第二存储器地址的第二请求; 将第一存储器地址和第二存储器地址与引用屏障地址的屏障指针进行比较，并分离迁移的地址和未迁移的地址; 响应于所述第一存储器地址位于所述屏障地址的未迁移侧，用指示所述第一寻址方案的第一标签来标记所述第一请求; 响应于所述第二存储器地址位于所述屏障地址的迁移侧，用指示所述第二寻址方案的第二标签来标记所述第二请求; 并将第一请求发送到第一存储器控制器单元（MCU），并将第二请求发送到第二MCU。

公开(公告)号：US20150278109A1

公开(公告)日：2015-10-01

申请号：US14675376

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Connie Wai Mun Cheung

IPC: G06F12/10

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.

Abstract translation: 一种用于寻址方案之间的存储器迁移的方法，包括：接收访问第一存储器地址的第一请求和访问第二存储器地址的第二请求; 将第一存储器地址和第二存储器地址与引用屏障地址的屏障指针进行比较，并分离迁移的地址和未迁移的地址; 响应于所述第一存储器地址位于所述屏障地址的未迁移侧，用指示所述第一寻址方案的第一标签来标记所述第一请求; 响应于所述第二存储器地址位于所述屏障地址的迁移侧，用指示所述第二寻址方案的第二标签来标记所述第二请求; 并将第一请求发送到第一存储器控制器单元（MCU），并将第二请求发送到第二MCU。