公开(公告)号：US09195531B2

公开(公告)日：2015-11-24

申请号：US13956171

申请日：2013-07-31

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Basant Vinaik

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/26 ,  G06F12/00 ,  G06F9/38

CPC classification number: G06F11/0751 ,  G06F9/38 ,  G06F11/0721 ,  G06F11/26 ,  G06F12/00

Abstract: A system and method for verifying that a processor design having caches conforms to a specific memory model. The caches might not be maintained coherent in real time. Specifically, the system and method make use of a checker that conforms to the memory model, a time-stamping scheme, and a store buffering scheme to identify a bug(s) in the processor design that violates the memory model and/or loads an incorrect value in response to a load instruction.

Abstract translation: 一种用于验证具有高速缓存的处理器设计符合特定存储器模型的系统和方法。 缓存可能不会保持实时一致。 具体地说，系统和方法利用符合存储器模型的检验器，时间戳方案和存储缓冲方案来识别违反存储器模型的处理器设计中的错误和/或加载 响应于加载指令的值不正确。

公开(公告)号：US20140215157A1

公开(公告)日：2014-07-31

申请号：US13754700

申请日：2013-01-30

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Mark S. Moir ,  Paul N. Loewenstein ,  David Dice

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F9/30047 ,  G06F11/3037 ,  G06F11/3096 ,  G06F12/0831 ,  G06F2201/885

Abstract: A system and method for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. More specifically, the disclosed embodiments provide a system that notifies a waiting thread when a targeted store is directed to monitored memory locations. During operation, the system receives a targeted store which is directed to a specific cache in a shared-memory multiprocessor system. In response, the system examines a destination address for the targeted store to determine whether the targeted store is directed to a monitored memory location which is being monitored for a thread associated with the specific cache. If so, the system informs the thread about the targeted store.

Abstract translation: 用于在共享存储器多处理器中支持目标存储的系统和方法。 目标商店使得第一处理器能够将要存储在第二处理器的高速缓冲存储器中的高速缓存行推送。 这消除了对多个高速缓存相干操作的需要，以将高速缓存行从第一处理器传送到第二处理器。 更具体地，所公开的实施例提供了当目标商店被引导到被监视的存储器位置时通知等待线程的系统。 在操作期间，系统接收目标商店，其被定向到共享存储器多处理器系统中的特定高速缓存。 作为响应，系统检查目标商店的目的地地址，以确定目标商店是否被定向到被监视的与特定高速缓存相关联的线程的监视的存储器位置。 如果是这样，系统通知线程有关目标商店。

公开(公告)号：US09836326B2

公开(公告)日：2017-12-05

申请号：US14675351

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： David Richard Smentek ,  Kathirgamar Aingaran ,  Sumti Jairath ,  Manling Yang ,  Serena Wing Yee Leung ,  Paul N. Loewenstein

IPC: G06F12/00 ,  G06F9/50 ,  G06F12/0817 ,  G06F12/0813 ,  G06F12/0831

CPC classification number: G06F9/5016 ,  G06F12/0813 ,  G06F12/0822 ,  G06F12/0831

Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.

公开(公告)号：US09160370B2

公开(公告)日：2015-10-13

申请号：US14146496

申请日：2014-01-02

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein

IPC: H03M13/00 ,  H03M13/15

CPC classification number: H03M13/151 ,  H03M13/152 ,  H03M13/2906

Abstract: A memory system is described that provides error detection and correction after a failure of a memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C-2 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and an inner check bit column including X inner check bits. The inner check bits are defined to cover bits in the array according to a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system. Moreover, each column is stored in a different memory component, and the check bits are generated from the data bits to provide block-level detection and correction for both memory errors and a failed memory component.

Abstract translation: 描述了在存储器组件故障之后提供错误检测和校正的存储器系统。 存储器系统中的每个数据块包括逻辑上组织成R行和C列的位阵列，包括包含数据位的C-2数据位列，包括每行R行的行奇偶校验位的行校验位列 在块中，以及包括X内部校验位的内部校验位列。 内部校验位被定义为根据一组校验向量来覆盖阵列中的比特，其中每个校验向量与阵列中的不同比特相关联，并且是Res（P）的元素，残差系统。 此外，每列存储在不同的存储器组件中，并且从数据位产生校验位，以提供对于存储器错误和故障存储器组件的块级检测和校正。

公开(公告)号：US08972663B2

公开(公告)日：2015-03-03

申请号：US13830967

申请日：2013-03-14

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Stephen E. Phillips ,  David Richard Smentek ,  Connie Wai Mun Cheung ,  Serena Wing Yee Leung ,  Damien Walker ,  Ramaswamy Sivaramakrishnan

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828

Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.

Abstract translation: 一种用于高速缓存一致性的方法，包括：通过部分有序请求网络（RN）的请求者缓存（RC）广播对多个从高速缓存的高速缓存线的对等（P2P）请求; 当P2P请求正在等待时，由RC接收和通过RN接收来自网关的高速缓存行的转发请求; 由所述RC接收所述转发请求后，从所述多个从属高速缓存中接收对所述P2P请求的多个响应; 在所述RC中设置所述高速缓存行的处理器内状态，其中所述处理器内状态还指定所述高速缓存行的处理器间状态; 以及在设置处理器内状态之后，在P2P请求完成之后，由RC发出对转发请求的响应; 以及响应于发出对所转发的请求的响应，由RC修改处理器内状态。

公开(公告)号：US20150278092A1

公开(公告)日：2015-10-01

申请号：US14675351

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： David Richard Smentek ,  Kathirgamar Aingaran ,  Sumti Jairath ,  Manling Yang ,  Serena Wing Yee Leung ,  Paul N. Loewenstein

IPC: G06F12/08

CPC classification number: G06F9/5016 ,  G06F12/0813 ,  G06F12/0822 ,  G06F12/0831

Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.

Abstract translation: 一种用于分配数据流的方法和系统，包括在分配器处接收数据流。 数据流包括与存储器地址相关联的存储器地址和数据。 该方法还包括由分配器检查数据流以确定数据流是软分配数据流，然后基于确定从分配器发送多个写入探测到多个高速缓存 ，其中所述多个写入探针中的每个写入探针包括所述存储器地址的至少一部分。 另外，该方法包括在分配器处响应于多个写入探测器的写入探针而从多个高速缓存的高速缓存中接收高速缓存行当前确认，并且响应于存在的高速缓存行指示分配器 确认数据流到缓存的数据。

公开(公告)号：US20150188571A1

公开(公告)日：2015-07-02

申请号：US14146496

申请日：2014-01-02

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein

IPC: H03M13/15

CPC classification number: H03M13/151 ,  H03M13/152 ,  H03M13/2906

Abstract: A memory system is described that provides error detection and correction after a failure of a memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C-2 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and an inner check bit column including X inner check bits. The inner check bits are defined to cover bits in the array according to a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system. Moreover, each column is stored in a different memory component, and the check bits are generated from the data bits to provide block-level detection and correction for both memory errors and a failed memory component.

Abstract translation: 描述了在存储器组件故障之后提供错误检测和校正的存储器系统。 存储器系统中的每个数据块包括逻辑上组织成R行和C列的位阵列，包括包含数据位的C-2数据位列，包括每行R行的行奇偶校验位的行校验位列 在块中，以及包括X内部校验位的内部校验位列。 内部校验位被定义为根据一组校验向量来覆盖阵列中的比特，其中每个校验向量与阵列中的不同比特相关联，并且是Res（P）的元素，残差系统。 此外，每列存储在不同的存储器组件中，并且从数据位产生校验位，以提供对于存储器错误和故障存储器组件的块级检测和校正。

公开(公告)号：US20140181420A1

公开(公告)日：2014-06-26

申请号：US13758491

申请日：2013-02-04

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Thomas M. Wicki ,  Stephen E. Phillips ,  Nicholas E. Aneshansley ,  Ramaswamy Sivaramakrishnan ,  Paul N. Loewenstein

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F11/07 ,  G06F11/14 ,  G06F12/0824

Abstract: A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.

Abstract translation: 系统包括多个处理器，每个处理器包括高速缓冲存储器。 该系统还包括耦合到处理器的多个目录控制器。 每个目录控制器可以被配置为管理对应的高速缓存一致性目录。 每个高速缓存一致性目录可以被配置为跟踪相应的一组存储器地址。 每个处理器可以配置有指示由每个高速缓存一致性目录跟踪的对应的一组存储器地址的信息。 这种系统中的目录冗余操作可以包括识别高速缓存一致性目录之一的故障; 重新分配先前由非故障高速缓存一致性目录中的失败的高速缓存一致性目录跟踪的存储器地址集; 以及用描述非故障高速缓存一致性目录中的存储器地址集的重新分配的信息重新配置每个处理器。

公开(公告)号：US10423482B2

公开(公告)日：2019-09-24

申请号：US15458408

申请日：2017-03-14

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/29 ,  H03M13/13 ,  H03M13/15

Abstract: The disclosed embodiments provide a memory system that provides error detection and correction. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C−M−1 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and M inner check bit columns that collectively include MR inner check bits. These inner check bits are defined to cover bits in the array in accordance with a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system comprising a set of polynomials with GF(2) coefficients modulo a polynomial P with GF(2) coefficients, wherein each column is associated with a different pin in a memory module interface, and wherein the check bits are generated from the data bits to facilitate block-level detection and correction for errors that arise during the transmission. During operation, the system transmits a block of data from the memory. Next, the system uses an error-detection circuit to examine the block of data, and determine whether an error has occurred during the transmission based on the examination.

公开(公告)号：US10223116B2

公开(公告)日：2019-03-05

申请号：US13828555

申请日：2013-03-14

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  John G. Johnson ,  Kathirgamar Aingaran ,  Zoran Radovic

IPC: G06F12/08 ,  G06F12/12 ,  G06F9/30 ,  G06F17/30 ,  G06F9/54 ,  G06F9/38 ,  G06F12/0804 ,  G06F15/173 ,  G06F12/0817 ,  G06F12/14 ,  G06F21/62 ,  H04L29/06 ,  G06F15/78 ,  G06F13/10 ,  G06F13/362 ,  G06F13/40

Abstract: A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, load and store instructions that target the mirrored memory portion of a sharer node are trapped, and store instructions that target the shared memory portion of a home node are trapped. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no “dirty” data is transferred between sharer nodes. As a result, the failure of one node will not cause the failure of another node or the failure of the entire system.