Erasure style LDPC rate matching for TB over multiple slots

    公开(公告)号:US12166581B2

    公开(公告)日:2024-12-10

    申请号:US17664630

    申请日:2022-05-23

    Abstract: Methods, apparatuses, and computer-readable storage medium for rate matching for TBoMS are provided. An example method includes calculating a slot length for each UL slot of a plurality of UL slots, the slot length for each UL slot being associated with a plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single TB or a single rate matching. The example method may include allocating one or more bits of the plurality of rate matching output bits for a modulation process. The example method may include refraining allocating at least one bit of the plurality of rate matching output bits for the modulation process, the at least one bit corresponding to UCI multiplexing.

    Priority based mapping of encoded bits to symbols

    公开(公告)号:US12166578B2

    公开(公告)日:2024-12-10

    申请号:US17657938

    申请日:2022-04-04

    Abstract: A new radio (NR) bit prioritization procedure that may be executed by a UE and a base station is disclosed, resulting in transmission and reception of modulation symbols having prioritized bits. For example, a transmitter may encode a code block using low-density parity-check code to generate a stream of encoded bits. The transmitter may arrange the encoded bits in one or more modulation symbols according to a relative priority of the encoded bits. The highest priority bits may be located in the most significant bits of the modulation symbol, and therefore be less likely to experience errors. A receiver may receive the modulation symbols and reorder the encoded bits according to the coding scheme based on the relative priority prior to decoding the encoded bits. The prioritization of the bits within the modulation symbols may provide improved block error rates over sequential mapping of encoded bits to symbols.

    Half duplex handling in carrier aggregation

    公开(公告)号:US11997053B2

    公开(公告)日:2024-05-28

    申请号:US16691434

    申请日:2019-11-21

    CPC classification number: H04L5/16 H04L5/0051 H04L5/0055 H04W72/0446

    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive a first slot format configuration for a first serving cell for a set of transmission time intervals (TTIs) including a first TTI and receive a second slot format configuration for the first serving cell for the first TTI which is different from the first slot format configuration. The UE may determine, based on priorities of the slot format configurations, a first communication direction for the first serving cell for the first TTI. The UE may identify, for a second serving cell for the first TTI, a second communication direction indicated by one or more slot format configurations for the second serving cell. The UE may determine whether to communicate on the second serving cell for the first TTI according to the one or more slot format configurations for the second serving cell.

Patent Agency Ranking