公开(公告)号：US11493970B2

公开(公告)日：2022-11-08

申请号：US17085505

申请日：2020-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Kong Yee Chun ,  Chandan Agarwalla ,  Dipti Ranjan Pal ,  Kumar Kanti Ghosh ,  Matthew Severson ,  Nilanjan Banerjee ,  Joshua Stubbs

IPC: G06F1/26 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/3287

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

公开(公告)号：US12093096B2

公开(公告)日：2024-09-17

申请号：US18082518

申请日：2022-12-15

Applicant: QUALCOMM Incorporated

Inventor： Aravind Bhaskara ,  Zhurang Zhao ,  Kiran Bhagwat ,  Michael Tipton ,  Joshua Stubbs ,  Jyotirmoy Das ,  Thomas Tang

IPC: G06F1/00 ,  G06F1/08 ,  G06F1/26 ,  G06F1/3203

CPC classification number: G06F1/26 ,  G06F1/08 ,  G06F1/3203

Abstract: Various dynamic voltage and frequency scaling (DVFS) techniques can optimize the high voltage residency of a device containing multiple processing cores that share a voltage rail. The DVFS techniques described herein can reduce the high voltage residency (duration) of the voltage rail by aligning the high frequency duration of multiple cores sharing the same voltage rail.

公开(公告)号：US12250454B2

公开(公告)日：2025-03-11

申请号：US18165189

申请日：2023-02-06

Applicant: QUALCOMM Incorporated

Inventor： Aravind Bhaskara ,  Tauseef Kazi ,  Zhurang Zhao ,  Rohan Desai ,  Michael Tipton ,  Joshua Stubbs ,  Kiran Bhagwat ,  Pavan Kumar Chilamkurthi

IPC: H04N23/65 ,  H04N25/71

Abstract: Systems, methods, and computer-readable media are provided for camera dynamic voting to optimize fast sensor mode power. In some examples, a computing device can obtain, based on performing dynamic voting, a plurality of votes associated with a plurality of components sharing a power source. The computing device can determine a voting result based on the plurality of votes. The computing device can increase or decreasing a clock rate and a voltage for the power source based on the voting result to produce an updated clock rate and an updated voltage. The computing device can then apply the updated clock rate and the updated voltage to an image processor.

公开(公告)号：US20190266098A1

公开(公告)日：2019-08-29

申请号：US15908637

申请日：2018-02-28

Applicant: QUALCOMM Incorporated

Inventor： Andrew Torchalski ,  Edwin Jose ,  Joshua Stubbs

IPC: G06F12/0891 ,  G06F3/06

Abstract: Various embodiments include methods and devices for implementing progressive flush of a cache memory of a computing device. Various embodiments may include determining an activity state of a region of the cache memory, issuing a start cache memory flush command in response to determining that the activity state of the region is idle, flushing the region in response to the start cache memory flush command, determining that the activity state of the region is active, issuing an abort cache memory flush command in response to determining that the activity state of the region is active, and aborting flushing the region in response to the abort cache memory flush command.

公开(公告)号：US09927866B2

公开(公告)日：2018-03-27

申请号：US14187270

申请日：2014-02-22

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Yiran Li ,  Inho Hwang ,  Young Hoon Kang ,  Joshua Stubbs ,  Sean Sweeney ,  R. Nicholson Gibson ,  Andrew J. Frantz

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/324 ,  Y02D10/172

Abstract: A method and system for optimizing a core voltage level of a portable computing device (“PCD”) and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values is determined for a plurality of subcomponents within the PCD. Next, a reduced set of voltage values may be calculated with a voltage aggregator based on the plurality of voltage values. An optimized voltage level for a shared power domain may then be determined by a voltage optimizer within the PCD from the reduced set of voltage values. A shared power domain may then be set to the optimized voltage level. Subsequently, an operating frequency of each subcomponent may be optimized with a frequency performance enhancer based on the optimized voltage level. An optimal power collapse duration may also be calculated by the frequency performance enhancer and set for each subcomponent from the optimal frequency.