-
公开(公告)号：US12229864B2
公开(公告)日：2025-02-18
申请号：US17817815
申请日：2022-08-05
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Eric Demers , Andrew Evan Gruber , Chun Yu , Baoguang Yang , Chihong Zhang , Yuehai Du , Avinash Seetharamaiah , Jonnala Gadda Nagendra Kumar , Gang Zhong , Zilin Ying , Fei Wei
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.
-
公开(公告)号：US11094032B2
公开(公告)日：2021-08-17
申请号：US16734252
申请日：2020-01-03
Applicant: QUALCOMM INCORPORATED
Inventor： Yun Du , Chun Yu , Andrew Evan Gruber , Zilin Ying , Baoguang Yang
Abstract: Methods, systems, and devices for image processing are described. A device may determine, based on a test operation, to terminate a first wave associated with a first slot of a set of slots. The device may update a terminated wave bit associated with the first slot based on the determination to terminate the first wave. In some aspects, the device may update a number of invocations field associated with the first wave based on the determination to terminate the first wave. The device may release the first slot based on updating the terminated wave bit and the number of invocations field. In some examples, the device may output the number of invocations field to a rendering backend of the device based on the terminated wave bit.
-
公开(公告)号：US20210183005A1
公开(公告)日：2021-06-17
申请号：US16714052
申请日：2019-12-13
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Andrew Evan Gruber , Chihong Zhang , Gang Zhong , Jian Jiang , Fei Wei , Minjie Huang , Zilin Ying , Yang Xia , Jing Han , Chun Yu , Eric Demers
Abstract: Methods, systems, and devices for graphic processing are described. The methods, systems, and devices may include or be associated with identifying a graphics instruction, determining that the graphics instruction is alias enabled for the device, partitioning an alias lookup table into one or more slots, allocating a slot of the alias lookup table based on the partitioning and determining that the graphics instruction is alias enabled, generating an alias instruction based on allocating the slot of the alias lookup table and determining that the graphics instruction is alias enabled, and processing the alias instruction.
-
公开(公告)号：US10558460B2
公开(公告)日：2020-02-11
申请号：US15379195
申请日：2016-12-14
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Liang Han , Lin Chen , Chihong Zhang , Hongjiang Shang , Jing Wu , Zilin Ying , Chun Yu , Guofang Jiao , Andrew Gruber , Eric Demers
Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.
-
公开(公告)号：US20240078735A1
公开(公告)日：2024-03-07
申请号：US18067837
申请日：2022-12-19
Applicant: QUALCOMM Incorporated
Inventor： Jian Liang , Andrew Evan Gruber , Tao Wang , Xuefeng Tang , Vishwanath Shashikant Nikam , Nigel Poole , Kalyan Kumar Bhiravabhatla , Fei Xu , Zilin Ying
IPC: G06T15/00
CPC classification number: G06T15/005
Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.
-
Patent Agency Ranking
公开(公告)号：US11055808B2
公开(公告)日：2021-07-06
申请号：US16455641
申请日：2019-06-27
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Andrew Evan Gruber , Chun Yu , Zilin Ying
Abstract: The present disclosure relates to methods and apparatus for graphics processing. In some aspects, the apparatus can determine one or more context states of at least one context register in each of multiple wave slots. The apparatus can also send information corresponding to the one or more context states in one of the multiple wave slots to a context queue. Further, the apparatus can convert the information corresponding to the one or more context states to context information compatible with the context queue. The apparatus can also store the context information compatible with the context queue in the context queue. In some aspects, the apparatus can send the context information compatible with the context queue to one of the multiple wave slots. Additionally, the apparatus can convert the context information compatible with the context queue to the information corresponding to the one or more context states.
-
公开(公告)号：US20180165092A1
公开(公告)日：2018-06-14
申请号：US15379195
申请日：2016-12-14
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Liang Han , Lin Chen , Chihong Zhang , Hongjiang Shang , Jing Wu , Zilin Ying , Chun Yu , Guofang Jiao , Andrew Gruber , Eric Demers
Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.
-
公开(公告)号：US12056790B2
公开(公告)日：2024-08-06
申请号：US17758219
申请日：2020-01-31
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Andrew Evan Gruber , Chun Yu , Chihong Zhang , Thomas Edwin Frisinger , Richard Hammerstone , Zilin Ying , Heng Qi , Quanquan Xu , Sheng Gu
IPC: G06T1/60
CPC classification number: G06T1/60
Abstract: The present disclosure relates to methods and apparatus for graphics processing. For example, disclosed techniques facilitate improving bindless state processing at a graphics processor. Aspects of the present disclosure can receive, at a graphics processor, a shader program including a preamble section and a main instructions section. Aspects of the present disclosure can also execute, with a scalar processor dedicated to processing preamble sections, instructions of the preamble section to implement a bindless mechanism for loading constant data associated with the shader program. Additionally, aspects of the present disclosure can distribute the main instructions section and the constant data to a streaming processor for executing the shader program.
-
公开(公告)号：US11954758B2
公开(公告)日：2024-04-09
申请号：US17652478
申请日：2022-02-24
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Andrew Evan Gruber , Zilin Ying , Chunling Hu , Baoguang Yang , Yang Xia , Gang Zhong , Chun Yu , Eric Demers
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for dynamic wave pairing. A graphics processor may allocate one or more GPU workloads to one or more wave slots of a plurality of wave slots. The graphics processor may select a first execution slot of a plurality of execution slots for executing the one or more GPU workloads. The selection may be based on one of a plurality of granularities. The graphics processor may execute, at the selected first execution slot, the one or more GPU workloads at the one of the plurality of granularities.
-
公开(公告)号：US11204765B1
公开(公告)日：2021-12-21
申请号：US17003600
申请日：2020-08-26
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Fei Wei , Gang Zhong , Minjie Huang , Jian Jiang , Zilin Ying , Baoguang Yang , Yang Xia , Jing Han , Liangxiao Hu , Chihong Zhang , Chun Yu , Andrew Evan Gruber , Eric Demers
Abstract: A graphics processing unit (GPU) utilizes block general purpose registers (bGPRs) to load multiple waves of samples for an instruction group into a processing pipeline and receive processed samples from the pipeline. The GPU acquires a credit for the bGPR for execution of the instruction group for a first wave using a persistent GPR and the bGPR. The GPU refunds the credit upon loading the first wave into the pipeline. The GPU executes a subsequent wave for the instruction group to load samples to the pipeline when at least one credit is available and the pipeline is processing the first wave. The GPU stores an indication of each wave that has been loaded into the pipeline in a queue. The GPU returns samples for a next wave in the queue from the pipeline to the bGPR for further processing when the physical slot of the bGPR is available.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.013 seconds)
