公开(公告)号：US11855198B2

公开(公告)日：2023-12-26

申请号：US16844479

申请日：2020-04-09

Applicant: QUALCOMM Incorporated

Inventor： Chenjie Tang ,  Ye Lu ,  Peijie Feng ,  Junjing Bao

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42316 ,  H01L29/66462

Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

公开(公告)号：US11380685B2

公开(公告)日：2022-07-05

申请号：US17061941

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Ye Lu ,  Chenjie Tang ,  Peijie Feng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/092

Abstract: Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.

公开(公告)号：US11189617B2

公开(公告)日：2021-11-30

申请号：US16774278

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Ye Lu ,  Junjing Bao ,  Chenjie Tang

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10 ,  H01L27/092 ,  H01L29/49 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306

Abstract: Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.

公开(公告)号：US11411092B2

公开(公告)日：2022-08-09

申请号：US16868376

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Ye Lu ,  Peijie Feng ,  Chenjie Tang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L21/02 ,  H01L21/764

Abstract: An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

公开(公告)号：US20210320197A1

公开(公告)日：2021-10-14

申请号：US16844479

申请日：2020-04-09

Applicant: QUALCOMM Incorporated

Inventor： Chenjie Tang ,  Ye Lu ,  Peijie Feng ,  Junjing Bao

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L21/02

Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.