公开(公告)号：US20170336840A1

公开(公告)日：2017-11-23

申请号：US15162452

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

公开(公告)号：US20140013295A1

公开(公告)日：2014-01-09

申请号：US14022310

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Li Qiu

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5077

Abstract: A method includes detecting channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value. The method also includes automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.

Abstract translation: 一种方法包括检测集成电路中的宏之间的通道。 每个通道与两个宏之间的区域相关联，使得该区域的最短距离满足阈值。 该方法还包括在至少一个信道内自动添加至少一个电力线以满足至少一个信道内的电力完整性问题。 当具有相反极性的两个电力线被耦合以向至少一个通道内的装置提供电力时，满足电力完整性问题。

公开(公告)号：US20130080848A1

公开(公告)日：2013-03-28

申请号：US13680312

申请日：2012-11-19

Applicant: QUALCOMM Incorporated

Inventor： Frederick C. Jen ,  Li Qiu ,  Hsiu C. Ma ,  Calvin V. Ho ,  Xiang M. Song ,  Hsiaohui Wu ,  Thomas E. Little

IPC: G01R31/3177 ,  H03K19/00

CPC classification number: G01R31/3177 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/14 ,  G06F2217/78 ,  H03K19/00

Abstract: A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a circuit includes a combinational logic portion including a logic path including a test isolation gate between a starting element and an ending element. The logic path includes at least a first gate element between the starting element and the test isolation gate. The logic path also includes at least a second gate element between the test isolation gate and the ending element. The starting element and the ending element are coupled to be tested via a scan chain test process during a test mode. In the test mode, an output of the second gate element is fixed at a constant logic level.

Abstract translation: 公开了一种选择要修改为测试隔离门的门的系统和方法。 在特定实施例中，电路包括组合逻辑部分，其包括逻辑路径，逻辑路径包括起始元件和结束元件之间的测试隔离栅极。 逻辑路径至少包括起始元件和测试隔离栅极之间的第一栅极元件。 逻辑路径还包括测试隔离栅极和结束元件之间的至少第二栅极元件。 起始元件和结束元件耦合以在测试模式期间经由扫描链测试过程进行测试。 在测试模式中，第二门元件的输出被固定在恒定的逻辑电平。

公开(公告)号：US20170336845A1

公开(公告)日：2017-11-23

申请号：US15162371

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/28 ,  G06T1/20

CPC classification number: G06F1/28 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78 ,  G06T1/20 ,  G06T2200/28 ,  H01L23/525 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2027/11881

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

公开(公告)号：US10394299B2

公开(公告)日：2019-08-27

申请号：US15162371

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/28 ,  G06T1/20 ,  G06F17/50 ,  H01L23/525 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

公开(公告)号：US09958918B2

公开(公告)日：2018-05-01

申请号：US15162452

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/00 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.