APPARATUS FOR DESIGN FOR TESTABILITY OF MULTIPORT REGISTER ARRAYS

    公开(公告)号:US20180019734A1

    公开(公告)日:2018-01-18

    申请号:US15207800

    申请日:2016-07-12

    Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

    AREA EFFICIENT MULTIPORT BITCELL
    2.
    发明申请
    AREA EFFICIENT MULTIPORT BITCELL 审中-公开
    区域高效多点比特

    公开(公告)号:US20150221346A1

    公开(公告)日:2015-08-06

    申请号:US14173788

    申请日:2014-02-05

    Abstract: A multiport bitcell apparatus includes a plurality of word lines for enabling writing and reading operations. The word lines include a first set of word lines extending across the bitcell on a first metal layer. The word lines further include a second set of word lines extending across the bitcell on a second metal layer. The word lines further include a third set of word lines extending across the bitcell on both the first metal layer and the second metal layer. The third set of word lines may include a first word line that extends on a first metal track and a second metal track, and a second word line that extends on the second metal track and a third metal track. The first metal layer may be an M2 layer and the second metal layer may be an M3 layer.

    Abstract translation: 多端口位单元装置包括用于使能写入和读取操作的多个字线。 字线包括在第一金属层上跨越位单元延伸的第一组字线。 字线还包括在第二金属层上跨越位单元延伸的第二组字线。 字线还包括在第一金属层和第二金属层两者上跨越位单元延伸的第三组字线。 第三组字线可以包括在第一金属轨道和第二金属轨道上延伸的第一字线,以及在第二金属轨道和第三金属轨道上延伸的第二字线。 第一金属层可以是M2层,第二金属层可以是M3层。

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