公开(公告)号：US20250062754A1

公开(公告)日：2025-02-20

申请号：US18449552

申请日：2023-08-14

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Dongwon SEO ,  Bhushan Shanti ASURI ,  Ibrahim Ramez CHAMAS ,  Huan WANG ,  Zhiheng WANG ,  Reza RODD

IPC: H03K5/01 ,  H03K19/20

Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

公开(公告)号：US20210081348A1

公开(公告)日：2021-03-18

申请号：US17003724

申请日：2020-08-26

Applicant: QUALCOMM Incorporated

Inventor： Reza RODD ,  Scott DAVENPORT ,  Umesh SRIKANTIAH ,  ZhenQi CHEN

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

公开(公告)号：US20210081340A1

公开(公告)日：2021-03-18

申请号：US17003697

申请日：2020-08-26

Applicant: QUALCOMM Incorporated

Inventor： Reza RODD ,  Scott DAVENPORT ,  Umesh SRIKANTIAH ,  ZhenQi CHEN

IPC: G06F13/20 ,  H04L29/08 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.