公开(公告)号：US20190288722A1

公开(公告)日：2019-09-19

申请号：US15962865

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti ASURI ,  Krishnaswamy THIAGARAJAN ,  Ashok SWAMINATHAN ,  Shahin MEHDIZAD TALEIE ,  Yen-Wei CHANG ,  Vinod PANIKKATH ,  Sameer Vasantlal VORA ,  Ayush MITTAL ,  Tonmoy BISWAS ,  Sy-Chyuan HWU ,  Zhilong TANG ,  Ibrahim CHAMAS ,  Ping Wing LAI ,  Behnam SEDIGHI ,  Dongwon SEO ,  Nitz SAPUTRA

IPC: H04B1/04 ,  H04B1/00 ,  H04L27/20

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

公开(公告)号：US20220416804A1

公开(公告)日：2022-12-29

申请号：US17359918

申请日：2021-06-28

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Dongwon SEO ,  Ashok SWAMINATHAN ,  Gurkanwal Singh SAHOTA ,  Andrew WEIL ,  Haibo FEI

IPC: H03M1/74 ,  H03M1/50 ,  H03M1/78 ,  H03M1/46

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

公开(公告)号：US20190383924A1

公开(公告)日：2019-12-19

申请号：US16012193

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Chen JIANG ,  Dongwon SEO ,  Udara FERNANDO ,  Shrenik PATEL ,  Roberto RIMINI ,  Anant GUPTA

IPC: G01S13/34 ,  G01S13/02 ,  H04L27/36 ,  H04L27/38 ,  H04B1/40 ,  H03M1/66

Abstract: Certain aspects of the present disclosure generally relate to a programmable multi-mode digital-to-analog converter (DAC) for generating a frequency-modulated signal. For example, certain aspects provide a circuit for sweeping a frequency of an output signal. The circuit generally includes a DAC having an input coupled to an input path of the circuit and an output coupled to an output path of the circuit, a first mixer selectively incorporated in the input path coupled to the input of the DAC, and a second mixer selectively incorporated in the output path coupled to the output of the DAC.

公开(公告)号：US20240204795A1

公开(公告)日：2024-06-20

申请号：US18068941

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Ashok SWAMINATHAN ,  Nitz SAPUTRA ,  Negar RASHIDI ,  Shahin MEHDIZAD TALEIE ,  Chinmaya MISHRA ,  Dongwon SEO ,  Jong Hyeon PARK ,  Sang-June PARK

IPC: H03M1/66 ,  H03M1/82

CPC classification number: H03M1/665 ,  H03M1/82

Abstract: Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

公开(公告)号：US20230097708A1

公开(公告)日：2023-03-30

申请号：US17448461

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Parisa MAHMOUDIDARYAN ,  Nitz SAPUTRA ,  Dongwon SEO ,  Shahin MEHDIZAD TALEIE

IPC: H03M1/06

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

公开(公告)号：US20250062754A1

公开(公告)日：2025-02-20

申请号：US18449552

申请日：2023-08-14

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Dongwon SEO ,  Bhushan Shanti ASURI ,  Ibrahim Ramez CHAMAS ,  Huan WANG ,  Zhiheng WANG ,  Reza RODD

IPC: H03K5/01 ,  H03K19/20

Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

公开(公告)号：US20200169266A1

公开(公告)日：2020-05-28

申请号：US16202723

申请日：2018-11-28

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Behnam SEDIGHI ,  Dongwon SEO ,  Parisa MAHMOUDIDARYAN ,  Bhushan Shanti ASURI ,  Sang-June PARK ,  Shrenik PATEL

IPC: H03M1/66

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.