公开(公告)号：US20170168853A1

公开(公告)日：2017-06-15

申请号：US15367567

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Sankaran Nampoothiri ,  Narasimhan Venkata Agaram ,  Nir Gerber ,  Subodh Singh

IPC: G06F9/44 ,  G06F1/32 ,  G06F13/24 ,  G06F3/06

CPC classification number: G06F9/4418 ,  G06F1/3206 ,  G06F1/3287 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/24

Abstract: Dynamic predictive wake-up techniques are disclosed. A central processing unit (CPU) may initiate an input/output (I/O) transfer. The CPU may ascertain if a predicted time for the transfer exceeds an amount of time required to enter and exit a low-power mode and enter the low-power mode after the transfer is initiated. An I/O controller may calculate how long the transfer will take and compare that calculation to a known exit latency associated with the CPU. The calculated value is decremented by the amount of the known exit latency and the I/O controller may generate an early wake command at the decremented value. The CPU receives the early wake command and wakes such that the CPU is awake and ready to process data at conclusion of the transfer.