公开(公告)号：US20170031838A1

公开(公告)日：2017-02-02

申请号：US14811296

申请日：2015-07-28

Applicant: QUALCOMM Incorporated

Inventor： Satyaki Mukherjee ,  Subodh Singh ,  Ajaykumar Shankargouda Patil ,  Thomas Zeng ,  Azzedine Touzni

IPC: G06F12/14 ,  G06F9/455

CPC classification number: G06F12/1441 ,  G06F9/45558 ,  G06F12/1009 ,  G06F21/53 ,  G06F21/85 ,  G06F2009/45587 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F2212/657

Abstract: Disclosed is a method for protecting virtual machine data at a peripheral subsystem connected to at least one processor configured to host a plurality of virtual machines. In the method, context information, including a virtual machine identifier (VMID), is received. The VMID is unique to one of the plurality of virtual machines. A storage bank of a plurality of storage banks is selected based on the VMID included in the received context information. Each storage bank of the plurality of storage banks uses a same bus address range. A data bus is connected to the selected storage bank.

Abstract translation: 公开了一种用于在与被配置为托管多个虚拟机的至少一个处理器连接的外围子系统上保护虚拟机数据的方法。 在该方法中，接收包括虚拟机标识符（VMID）的上下文信息。 VMID对于多个虚拟机之一是唯一的。 基于接收到的上下文信息中包含的VMID来选择多个存储体的存储体。 多个存储组的每个存储体使用相同的总线地址范围。 数据总线连接到选定的存储库。

公开(公告)号：US20140245076A1

公开(公告)日：2014-08-28

申请号：US13779627

申请日：2013-02-27

Applicant: QUALCOMM Incorporated

Inventor： Kapil Bansal ,  Girish Bhat ,  Subodh Singh ,  Victor Wong ,  Pradeep Atur

IPC: G06F11/30

CPC classification number: G06F11/0742 ,  G06F11/0757 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/366

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract translation: 一个或多个触发器可以耦合到便携式计算设备的芯片上的系统上的源。 来源监视系统的状态条件。 一个或多个触发器耦合到触发总线。 定序器引擎耦合到触发总线和通信总线。 定序器引擎从通信总线接收一个或多个指令，用于确定定序器引擎如何经由触发总线监视一个或多个触发，并在系统复位之前保留从一个或多个触发器接收到的数据。 然后，定序器引擎从一个或多个触发器接收数据，并将数据存储在本地存储器中。 响应于从一个或多个触发器接收数据，定序器引擎（如果编程的话）可以产生跟踪数据包，中断信号和通用输入/输出信号中的至少一个。

公开(公告)号：US09304844B2

公开(公告)日：2016-04-05

申请号：US13779627

申请日：2013-02-27

Applicant: QUALCOMM Incorporated

Inventor： Kapil Bansal ,  Girish Bhat ,  Subodh Singh ,  Victor Wong ,  Pradeep Atur

IPC: G06F11/36 ,  G06F11/07

CPC classification number: G06F11/0742 ,  G06F11/0757 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/366

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract translation: 一个或多个触发器可以耦合到便携式计算设备的芯片上的系统上的源。 来源监视系统的状态条件。 一个或多个触发器耦合到触发总线。 定序器引擎耦合到触发总线和通信总线。 定序器引擎从通信总线接收一个或多个指令，用于确定定序器引擎如何经由触发总线监视一个或多个触发，并在系统复位之前保留从一个或多个触发器接收到的数据。 然后，定序器引擎从一个或多个触发器接收数据，并将数据存储在本地存储器中。 响应于从一个或多个触发器接收数据，定序器引擎（如果编程的话）可以产生跟踪数据包，中断信号和通用输入/输出信号中的至少一个。

公开(公告)号：US20170168853A1

公开(公告)日：2017-06-15

申请号：US15367567

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Sankaran Nampoothiri ,  Narasimhan Venkata Agaram ,  Nir Gerber ,  Subodh Singh

IPC: G06F9/44 ,  G06F1/32 ,  G06F13/24 ,  G06F3/06

CPC classification number: G06F9/4418 ,  G06F1/3206 ,  G06F1/3287 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/24

Abstract: Dynamic predictive wake-up techniques are disclosed. A central processing unit (CPU) may initiate an input/output (I/O) transfer. The CPU may ascertain if a predicted time for the transfer exceeds an amount of time required to enter and exit a low-power mode and enter the low-power mode after the transfer is initiated. An I/O controller may calculate how long the transfer will take and compare that calculation to a known exit latency associated with the CPU. The calculated value is decremented by the amount of the known exit latency and the I/O controller may generate an early wake command at the decremented value. The CPU receives the early wake command and wakes such that the CPU is awake and ready to process data at conclusion of the transfer.