公开(公告)号：US20210200652A1

公开(公告)日：2021-07-01

申请号：US16727603

申请日：2019-12-26

Applicant: Quanta Computer Inc.

Inventor： Yu-Hsien LIAO ,  Han-Chuan TSAI

IPC: G06F11/273 ,  G06F11/22 ,  G06F13/36

Abstract: A system and method for providing a status indicator during a power-on self-test routine. A basic input output system is operable to execute the power-on self-test routine and output a status of the power-on self-test routine. A plurality of storage devices that each have an externally visible indicator. A controller is coupled to the basic input output system and the plurality of storage devices. The controller is operable to receive the status from the basic input output system and control the externally visible indicator of each of the storage devices in response to the status received from the basic input output system.

公开(公告)号：US20240220113A1

公开(公告)日：2024-07-04

申请号：US18147124

申请日：2022-12-28

Applicant: Quanta Computer Inc.

Inventor： Wei-Hung LIN ,  Yen-Ping TUNG ,  Han-Chuan TSAI

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679

Abstract: An example computer-implemented method for synchronously programming multiple memory modules includes sending one or more instructions to each of the memory modules to perform a first data operation associated with a computer software update. In response to determining that each of the memory modules have received the first instructions to perform the first data operation, time is spent waiting for the first data operation to be completed at each of the memory modules. One or more instructions are also sent to each of the memory modules to perform a second data operation associated with the computer software update. In response to determining that each of the memory modules have received the second instructions to perform the second data operation, time is spent waiting for the second data operation to be completed at each of the memory modules. Furthermore, the data is validated across the memory modules.

公开(公告)号：US20240193104A1

公开(公告)日：2024-06-13

申请号：US18156251

申请日：2023-01-18

Applicant: Quanta Computer Inc.

Inventor： Han-Chuan TSAI ,  Wei-Hung LIN ,  Yen-Ping TUNG ,  Sz-Chin SHIH

IPC: G06F13/16

CPC classification number: G06F13/1652 ,  G06F2213/0016 ,  G06F2213/3808

Abstract: A system and method for a configurable computer system architecture is disclosed. The computer system architecture includes a power distribution board including a configuration identification strapping. The architecture includes a first node having a first processor and a first baseboard management controller (BMC) coupled to the power distribution board via an internal communication channel. A second node, identical to the first node, has a second processor and a second BMC coupled to the power distribution board via the internal communication channel. The configuration identification strapping is one of a first configuration readable by the first and second BMCs with two nodes operating as independent devices, or a second configuration readable by the first and second BMCs with two nodes operating as a single device. The first BMC serves as a master BMC and the second BMC serves as a slave BMC in the second configuration.

公开(公告)号：US20210200650A1

公开(公告)日：2021-07-01

申请号：US16728925

申请日：2019-12-27

Applicant: Quanta Computer Inc.

Inventor： Yun-Ting CIOU ,  Han-Chuan TSAI

IPC: G06F11/22 ,  G06F9/4401 ,  G08B5/36

Abstract: A system and method for providing status information during a power-on self-test routine. The system includes a basic input output system operable to execute the power-on self-test routine and output the status of the power-on self-test routine. The system includes an externally visible indicator such as a server chassis identify LED. A controller is coupled to the basic input output system and the externally visible indicator. The controller is operable to receive the status from the basic input output system, and to control the externally visible indicator in response to the status received from the basic input output system.