公开(公告)号：US20170344275A1

公开(公告)日：2017-11-30

申请号：US15529970

申请日：2015-12-18

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  Ely TSERN

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

公开(公告)号：US20160342487A1

公开(公告)日：2016-11-24

申请号：US15114795

申请日：2014-12-19

Applicant: RAMBUS INC.

Inventor： Frederick A. WARE ,  J. James TRINGALI ,  Ely TSERN

IPC: G06F11/14 ,  G06F3/06

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0685 ,  G06F2201/805 ,  G06F2201/84 ,  G11C7/20 ,  G11C14/0018

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

Abstract translation: 本文描述的实施例描述了在包括用于易失性存储器和非易失性存储器的两个或多个存储器技术的多层存储器系统中的非易失性存储器持久性的技术。