公开(公告)号：US20160049183A1

公开(公告)日：2016-02-18

申请号：US14824080

申请日：2015-08-12

Applicant: Rambus Inc.

Inventor： Soumya Bose ,  Navin Kumar Mishra ,  Abhilash Puzhankara ,  Mahabaleshwara Mahabaleshwara ,  Karthikeyan Swamiappan

IPC: G11C7/22 ,  G06N99/00

CPC classification number: G06N99/005 ,  G06F13/1668 ,  G11C7/06 ,  G11C7/067 ,  G11C7/1078 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

Abstract translation: 存储器控制器包括差分接收器电路，用于接收差分数据选通信号对，并且基于差分数据选通信号对产生第一数据选通信号。 差分数据选通信号对包括第一信号和第二信号。 存储器控制器还包括用于接收差分数据选通信号对的第一信号的单端接收器电路，并且基于差分数据选通信号对的第一信号产生第二数据选通信号。 存储器控制器还包括用于产生用于选通第一数据选通信号的门控信号的电路，该电路基于第二数据选通信号产生门控信号。

公开(公告)号：US20150162061A1

公开(公告)日：2015-06-11

申请号：US14325140

申请日：2014-07-07

Applicant: RAMBUS INC.

Inventor： Liji Gopalakrishnan ,  Mahabaleshwara Mahabaleshwara

IPC: G11C7/22 ,  G11C29/02

CPC classification number: G11C29/023 ,  G06F11/1076 ,  G06F11/14 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028

Abstract: A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value.

Abstract translation: 存储器控制器包括用于确定一个或多个存储器件的相应参考电压值和延迟值的逻辑。 存储器控制器包括命令地址（CA）接口，用于向存储器件发送命令以将存储器件的参考电压值设置为测试值，数据接口将数据模式写入存储器件并读取 来自存储器件的数据模式，以及测试参考电压逻辑，以对从存储器件读取的数据模式的至少一部分执行密度检查，并且基于密度检查确定测试值是否是潜在的参考电压值。 可以使用从一个或多个潜在参考电压值中选择的操作参考电压值来确定延迟值。

公开(公告)号：US09514420B2

公开(公告)日：2016-12-06

申请号：US14824080

申请日：2015-08-12

Applicant: Rambus Inc.

Inventor： Soumya Bose ,  Navin Kumar Mishra ,  Abhilash Puzhankara ,  Mahabaleshwara Mahabaleshwara ,  Karthikeyan Swamiappan

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06 ,  G11C7/08 ,  G06N99/00 ,  G06F13/16 ,  G11C11/4096

CPC classification number: G06N99/005 ,  G06F13/1668 ,  G11C7/06 ,  G11C7/067 ,  G11C7/1078 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

Abstract translation: 存储器控制器包括差分接收器电路，用于接收差分数据选通信号对，并且基于差分数据选通信号对产生第一数据选通信号。 差分数据选通信号对包括第一信号和第二信号。 存储器控制器还包括用于接收差分数据选通信号对的第一信号的单端接收器电路，并且基于差分数据选通信号对的第一信号产生第二数据选通信号。 存储器控制器还包括用于产生用于选通第一数据选通信号的门控信号的电路，该电路基于第二数据选通信号产生门控信号。

公开(公告)号：US09287003B2

公开(公告)日：2016-03-15

申请号：US14325140

申请日：2014-07-07

Applicant: RAMBUS INC.

Inventor： Liji Gopalakrishnan ,  Mahabaleshwara Mahabaleshwara

IPC: G11C7/00 ,  G11C29/02 ,  G06F11/10 ,  G06F11/14

CPC classification number: G11C29/023 ,  G06F11/1076 ,  G06F11/14 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028

Abstract: A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value.

Abstract translation: 存储器控制器包括用于确定一个或多个存储器件的相应参考电压值和延迟值的逻辑。 存储器控制器包括命令地址（CA）接口，用于向存储器件发送命令以将存储器件的参考电压值设置为测试值，数据接口将数据模式写入存储器件并读取 来自存储器件的数据模式，以及测试参考电压逻辑，以对从存储器件读取的数据模式的至少一部分执行密度检查，并且基于密度检查确定测试值是否是潜在的参考电压值。 可以使用从一个或多个潜在参考电压值中选择的操作参考电压值来确定延迟值。