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公开(公告)号：US20190097413A1
公开(公告)日：2019-03-28
申请号：US16100305
申请日：2018-08-10
发明人： CHIA-WEI YU , HUNG-CHE CHU , YUNG-TAI CHEN
摘要： The present invention discloses an overvoltage-proof circuit capable of preventing damage caused by an overvoltage at moments of starting and/or stopping operation. An embodiment of the overvoltage-proof circuit includes a protected circuit and a protecting circuit. The protected circuit receives a power supply voltage to operate, and includes: a protected component, in which an upmost voltage that the protected component can withstand is lower than the power supply voltage; and at least one operational switch(es) operable to enable or disable the protected circuit according to an enabling signal. The protecting circuit is coupled to the protected component, and starts protecting the protected circuit from an overvoltage before a transition of the enabling signal, in which the overvoltage is greater than the upmost voltage.
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公开(公告)号：US20230006660A1
公开(公告)日：2023-01-05
申请号：US17727909
申请日：2022-04-25
发明人： CHIEN-HUI TSAI , HUNG-CHEN CHU , YUNG-TAI CHEN
IPC分类号： H03K3/037
摘要： A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.
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公开(公告)号：US20150103986A1
公开(公告)日：2015-04-16
申请号：US14316539
申请日：2014-06-26
发明人： YUNG-TAI CHEN , CHENG-HSIEN LI , HUNG-CHEN CHU , JIAN-RU LIN
CPC分类号： H04B3/20
摘要： This invention discloses a signal transmitting and receiving circuit of a digital subscriber line used for transmitting an output signal to a telecommunication loop or receiving an input signal from the telecommunication loop. The signal transmitting and receiving circuit comprises a transformer, which is coupled to the telecommunication loop; a signal transmitting module, which is coupled to the transformer, for generating the output signal; a signal receiving module, which is coupled to the transformer, for processing the input signal; an echo cancelling circuit, comprising passive components and having two ends, one of which is coupled to the signal transmitting module and the transformer, the other is coupled to the signal receiving module and the transformer. The output signal is transmitted to the telecommunication loop via the electromagnetic coupling of the transformer, and the input signal is received by the signal receiving module by the electromagnetic coupling of the transformer.
摘要翻译： 本发明公开了一种数字用户线路的信号发送和接收电路，用于向电信环路发送输出信号或从电信环路接收输入信号。 信号发射和接收电路包括耦合到电信环路的变压器; 信号发射模块，其耦合到所述变压器，用于产生所述输出信号; 信号接收模块，其耦合到所述变压器，用于处理所述输入信号; 回波消除电路，包括无源部件并具有两端，其中一端耦合到信号传输模块和变压器，另一端耦合到信号接收模块和变压器。 输出信号通过变压器的电磁耦合传输到电信环路，输入信号由变压器的电磁耦合由信号接收模块接收。
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公开(公告)号：US20230216493A1
公开(公告)日：2023-07-06
申请号：US18074825
申请日：2022-12-05
发明人： CHIEN-HUI TSAI , HUNG-CHEN CHU , YUNG-TAI CHEN
IPC分类号： H03K17/693 , H03K17/687 , H03H11/28
CPC分类号： H03K17/693 , H03K17/6872 , H03K17/6874 , H03H11/28
摘要： An output stage of an Ethernet transmitter is provided. The output stage is coupled to a resistor and includes a first output terminal, a second output terminal, a first transistor, and a first transistor group. The resistor is coupled between the first output terminal and the second output terminal. The first transistor has a first source, a first drain, and a first gate, the first source being coupled to a first reference voltage and the first drain being coupled to the second output terminal. The first transistor group is coupled to the first reference voltage and the first output terminal. The first transistor group includes multiple transistors which are connected in parallel, and the magnitude of the current flowing to the first output terminal is related to the number of transistors that are turned on.
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公开(公告)号：US20230006652A1
公开(公告)日：2023-01-05
申请号：US17727856
申请日：2022-04-25
发明人： CHIEN-HUI TSAI , HUNG-CHEN CHU , YUNG-TAI CHEN
摘要： A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.
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公开(公告)号：US20230291391A1
公开(公告)日：2023-09-14
申请号：US18115787
申请日：2023-03-01
发明人： HUNG-CHEN CHU , CHIEN-HUI TSAI , YUNG-TAI CHEN
IPC分类号： H03H11/28 , H03K17/567 , H03K17/58
CPC分类号： H03H11/28 , H03K17/567 , H03K17/58
摘要： A transmitter circuit is provided. The transmitter circuit has a first transmission node and a second transmission node and includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a driving circuit. The driving circuit includes a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group. The first resistor is coupled between a first output terminal and the first transmission node. The second resistor is coupled between a second output terminal and the second transmission node. The third resistor is coupled between a third output terminal and the first transmission node. The fourth resistor is coupled between a fourth output terminal and the second transmission node. The first, second, third, and fourth transistor groups are coupled to a first and a second reference voltages and electrically connected to the first, second, third, and fourth output terminals, respectively.
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