公开(公告)号：US20240128248A1

公开(公告)日：2024-04-18

申请号：US18365455

申请日：2023-08-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi MIYAKI ,  Takayuki IGARASHI

IPC: H01L25/16 ,  H01F27/28 ,  H01F27/30 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01F27/2804 ,  H01F27/306 ,  H01L24/32 ,  H01F27/324 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/32265 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2224/73265 ,  H01L2924/19042 ,  H01L2924/19104

Abstract: A semiconductor device includes an insulating substrate and an upper inductor that is formed on the insulating substrate and is a component of a transformer that performs contactless communication between different potentials. Here, the upper inductor is configured to be applied with a first potential. The upper inductor is formed so as to be magnetically coupled to a lower inductor that is configured to be applied with a second potential different from the first potential.

公开(公告)号：US20230369253A1

公开(公告)日：2023-11-16

申请号：US18181274

申请日：2023-03-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi MIYAKI

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a redistribution layer. The first semiconductor chip and the second semiconductor chip are arranged spaced apart from each other in a second direction orthogonal to a first direction. The redistribution layer is disposed across over the first semiconductor chip and the second semiconductor chip. The redistribution layer includes a first inductor and a second inductor. The first inductor and the second inductor are spaced apart and face each other in a third direction orthogonal to the first direction and the second direction. The first inductor and the second inductor are electrically connected to the first semiconductor chip and the second semiconductor chip, respectively. The first inductor and the second inductor are wound across over the first semiconductor chip and the second semiconductor chip in a plane orthogonal to the third direction.

公开(公告)号：US20230065171A1

公开(公告)日：2023-03-02

申请号：US17887184

申请日：2022-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi MIYAKI

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor device includes a first semiconductor chip in which a first multilayer wiring structure including a first coil and a second coil is formed and a second semiconductor chip in which a second multilayer wiring structure including a third coil and a fourth coil is formed. The second semiconductor chip is joined to the first semiconductor chip such that the first coil (second coil) and the third coil (fourth coil) are overlapped and the second semiconductor chip does not have an offset structure with respect to the first semiconductor chip. The second semiconductor chip is joined to the first semiconductor chip such that it is not overlapped with a pad for the first semiconductor chip and a pad for the second semiconductor chip.