公开(公告)号：US20230197827A1

公开(公告)日：2023-06-22

申请号：US18052382

申请日：2022-11-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Zhichao LIN ,  Koji OGATA ,  Yukio TAKAHASHI ,  Tomohiro IMAI ,  Tetsuya YOSHIDA

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/66348 ,  H01L29/7397 ,  H01L29/0638 ,  H01L29/0834 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/26513

Abstract: A gate electrode is formed inside a trench via a gate insulating film. The gate insulating film formed on a semiconductor substrate is removed. An insulating film is formed on the semiconductor substrate. A p-type base region is formed in the semiconductor substrate. An n-type emitter region is formed in the base region. Hydrogen annealing process is performed to the semiconductor substrate. A boundary between the base region and the emitter region is located at a position deeper than the insulating film formed between a side surface of the trench and the gate insulating film.

公开(公告)号：US20240030321A1

公开(公告)日：2024-01-25

申请号：US18331453

申请日：2023-06-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuho KAMADA ,  Koji OGATA ,  Kiyoyuki SATOU

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

Abstract: A semiconductor device includes an n-type semiconductor substrate, a trench, and a gate electrode formed in the trench via a gate insulating film. An absolute value of a difference between a thickness of the gate insulating film formed on a corner portion of the trench and a thickness of the gate insulating film formed on the bottom portion of the trench is smaller than an absolute value of a difference between the thickness of the gate insulating film formed on the corner portion of the trench and a thickness of the gate insulating film formed on the sidewall portion of the trench.

公开(公告)号：US20230411502A1

公开(公告)日：2023-12-21

申请号：US18185065

申请日：2023-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji OGATA ,  Tetsuya YOSHIDA ,  Yukio TAKAHASHI

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/66348 ,  H01L29/0696

Abstract: A semiconductor device includes an n-type semiconductor substrate, a trench, a gate electrode formed in the trench via the gate insulating film, a p-type base region formed in the semiconductor substrate, and an n-type emitter region formed in the base region. The trench extends in a Y direction, in a plan view. Adjacent ones of a plurality of emitter regions are formed to be spaced apart from each other by a distance, along the Y direction. The distance is wider than ⅕ of a width of each of the emitter regions in the Y direction and narrower than the width.

公开(公告)号：US20230411200A1

公开(公告)日：2023-12-21

申请号：US18191505

申请日：2023-03-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tsuyoshi KANAO ,  Koji OGATA

IPC: H01L21/683 ,  H01L21/66 ,  H01L21/304

CPC classification number: H01L21/6836 ,  H01L22/12 ,  H01L21/304 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method of manufacturing a semiconductor device includes: a grind step of forming a small thickness portion and a large thickness portion surrounding the small thickness portion in plan view by grinding a back surface of a semiconductor wafer; a preparation step of preparing a wafer holding member including a wafer placement surface and a back surface opposite to the wafer placement surface and having a larger thickness than a difference between a thickness of the large thickness portion and a thickness of the small thickness portion; and a placement step of placing the semiconductor wafer on the wafer holding member so that the small thickness portion of the semiconductor wafer and the wafer placement surface of the wafer holding member are in contact with each other on the back surface side of the semiconductor wafer.

公开(公告)号：US20170309728A1

公开(公告)日：2017-10-26

申请号：US15468862

申请日：2017-03-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya YOSHIDA ,  Tetsuo ITO ,  Koji OGATA ,  Hideki AONO

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/266 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66568 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/78603

Abstract: In a process of implanting ions of an n-type impurity for threshold control into a semiconductor substrate surrounded by an element isolation portion, a resist pattern is formed such that the resist pattern covers a divot formed at a boundary portion of the element isolation portion with an SOI layer. Thus, since ions of the n-type impurity are not implanted into the divot, an etching rate of the divot in a cleaning process or the like is not accelerated, and etching can be suppressed. As a result, a BOX layer is prevented from becoming thin, so that degradation of a TDDB characteristic of the BOX layer can be prevented.