公开(公告)号：US20230197827A1

公开(公告)日：2023-06-22

申请号：US18052382

申请日：2022-11-03

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Zhichao LIN ,  Koji OGATA ,  Yukio TAKAHASHI ,  Tomohiro IMAI ,  Tetsuya YOSHIDA

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/265

CPC分类号： H01L29/66348 ,  H01L29/7397 ,  H01L29/0638 ,  H01L29/0834 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/26513

摘要： A gate electrode is formed inside a trench via a gate insulating film. The gate insulating film formed on a semiconductor substrate is removed. An insulating film is formed on the semiconductor substrate. A p-type base region is formed in the semiconductor substrate. An n-type emitter region is formed in the base region. Hydrogen annealing process is performed to the semiconductor substrate. A boundary between the base region and the emitter region is located at a position deeper than the insulating film formed between a side surface of the trench and the gate insulating film.

公开(公告)号：US20220102538A1

公开(公告)日：2022-03-31

申请号：US17405733

申请日：2021-08-18

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yoshito NAKAZAWA ,  Tomohiro IMAI

IPC分类号： H01L29/739 ,  H01L29/66

摘要： A semiconductor device according to one embodiment includes an IGBT having a p-type collector layer and an n-type field stop layer on a back surface of a silicon substrate. The n-type field stop layer is selectively provided on an upper side of the p-type collector layer such that a first end portion of the n-type field stop layer is separated from a first side surface of the silicon substrate by a predetermined distance, and an n-type drift layer is provided between the first side surface of the silicon substrate and the first end portion of the n-type field stop layer. An impurity concentration of the n-type drift layer is lower than an impurity concentration of the n-type field stop layer.

公开(公告)号：US20240213357A1

公开(公告)日：2024-06-27

申请号：US18391388

申请日：2023-12-20

申请人： Renesas Electronics Corporation

发明人： Tomohiro IMAI ,  Yoshito NAKAZAWA

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/41708 ,  H01L29/66348

摘要： Performance of a semiconductor device is enhanced. A floating region covers a bottom surface of a trench in an active cell. In addition, the floating region covers a bottom surface of a trench in an inactive cell so as to reach a semiconductor substrate between a pair of trenches in the inactive cell. A distance between a base region and the floating region in the inactive cell is smaller than a distance between the base region and the floating region in the active cell.

公开(公告)号：US20230178639A1

公开(公告)日：2023-06-08

申请号：US17958787

申请日：2022-10-03

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Tomohiro IMAI

IPC分类号： H01L29/739 ,  H01L29/36 ,  H01L21/768

CPC分类号： H01L29/7394 ,  H01L29/36 ,  H01L21/76897 ,  H01L29/7397

摘要： An interlayer insulating film includes a first insulating film formed on a semiconductor layer and a second insulating film formed on the first insulating film. The first insulating film is a silicon oxide film and the second insulating film is a BPSG film. A thickness of the second insulating film is larger than a thickness of the first insulating film. A contact hole is formed of a first contact hole and a second contact hole. The first contact hole penetrates an emitter region and reaches a base region. The second contact hole is formed in the first insulating film and the second insulating and communicates with the first contact hole. An opening width of the second contact hole is larger than an opening width of the first contact hole.

公开(公告)号：US20220069111A1

公开(公告)日：2022-03-03

申请号：US17405648

申请日：2021-08-18

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Tomohiro IMAI ,  Yoshito NAKAZAWA ,  Katsumi EIKYU

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/66

摘要： An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

公开(公告)号：US20200066887A1

公开(公告)日：2020-02-27

申请号：US16543106

申请日：2019-08-16

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Tomohiro IMAI

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L29/417

摘要： An IGBT with improved switching characteristics is disclosed. The contact hole CH1 in which the emitter potential electrode EE is buried is formed at a position overlapping with the trench T 1 in which the gate electrode G 1 is buried in plan view. The upper surface of gate electrode G1 in trench T1 is retracted, and an interlayer insulating film IL2 is formed on the top of trench T1. Since the bottom of the contact hole CH1 is located on the interlayer insulating film IL2 in the trench T 1 and in the base region PB, the emitter potential electrode EE is not in contact with the gate electrode G 1.