公开(公告)号：US20170092555A1

公开(公告)日：2017-03-30

申请号：US15280308

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Hideki AONO ,  Makoto OGASAWARA ,  Naohito SUZUMURA ,  Tetsuya YOSHIDA

IPC: H01L21/66

CPC classification number: H01L22/34 ,  G01R31/2621 ,  G01R31/2628 ,  G01R31/2642 ,  H01L22/14 ,  H01L22/26 ,  H01L29/785

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

公开(公告)号：US20170063075A1

公开(公告)日：2017-03-02

申请号：US15216883

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Kan TAKEUCHI ,  Mitsuhiko IGARASHI ,  Makoto OGASAWARA

IPC: H02H3/16 ,  G01R31/02 ,  H02H3/02

CPC classification number: H02H3/16 ,  G01R31/025 ,  H02H3/04

Abstract: In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.

Abstract translation: 在半导体装置中，异常监视部基于第一功能模块与第一功能模块之间的第一节点处的电压变化的比较来检测是否从第一功能模块或第二功能模块产生异常泄漏电流 当第二电源开关处于关闭状态时，第二电源开关处于关闭状态时第二功能模块与第二电源开关之间的第二节点处的电压变化。

公开(公告)号：US20190198402A1

公开(公告)日：2019-06-27

申请号：US16291620

申请日：2019-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki AONO ,  Tetsuya YOSHIDA ,  Makoto OGASAWARA ,  Shinichi OKAMOTO

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/76237 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region. surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation legion and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

公开(公告)号：US20160141289A1

公开(公告)日：2016-05-19

申请号：US14934745

申请日：2015-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki AONO ,  Tetsuya YOSHIDA ,  Makoto OGASAWARA ,  Shinichi OKAMOTO

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/76237 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract translation: 提供具有提高的可靠性的半导体器件。 主要由氧化硅组成的元件隔离区被埋在形成于半导体衬底中的沟槽中。 由元件隔离区包围的有源区中的半导体衬底在其上具有用于MISFET的栅极经由栅极绝缘膜。 栅电极部分地延伸在元件隔离区上方，并且沟槽具有氮化的内表面。 在栅电极下方，氟被引入到元件隔离区域和MISFET的沟道区域之间的边界附近。