公开(公告)号：US20190363050A1

公开(公告)日：2019-11-28

申请号：US16405644

申请日：2019-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI ,  Kazuyuki NAKAGAWA ,  Keita TSUCHIYA ,  Yosuke KATSURA ,  Shinji KATAYAMA ,  Norio CHUJO ,  Masayoshi YAGYU ,  Yutaka UEMATSU

IPC: H01L23/538 ,  H05K1/02 ,  H04L25/02 ,  H01L23/66 ,  H01L23/498

Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

公开(公告)号：US20190198463A1

公开(公告)日：2019-06-27

申请号：US16192323

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Shinji KATAYAMA ,  Keita TSUCHIYA

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2224/16227

Abstract: A semiconductor device includes a semiconductor chip including a first circuit and a wiring substrate over which the semiconductor chip is mounted. The wiring substrate includes input signal wires transmitting an input signal to the semiconductor chip, output signal wires transmitting an output signal from the semiconductor chip, and first conductor planes supplied with a reference potential. When a wire cross-sectional area is defined as the cross-sectional area of each wire in a direction orthogonal to a direction in which the wire extends, the wire cross-sectional area of each input signal wire is smaller than the wire cross-sectional area of each output signal wire. In the thickness direction of the wiring substrate, each input signal wire is interposed between second conductor planes and third conductor planes each supplied with the reference potential. Between the output signal wires and the input signal wires, the third conductor planes are disposed.