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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250046741A1

    公开(公告)日：2025-02-06

    申请号：US18775102

    申请日：2024-07-17

    Applicant: Renesas Electronics Corporation

    Inventor： Keita TSUCHIYA ,  Shuuichi KARIYAZAKI ,  Kazuo SAKAMOTO

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/528

    Abstract: The performance of a semiconductor device can be improved. A plurality of protruding electrodes of a semiconductor chip includes: a plurality of first protruding electrodes arranged at positions overlapping a first region of an insulating layer, a plurality of second protruding electrodes arranged at positions overlapping a second region of the insulating layer, and a plurality of third protruding electrodes arranged at positions overlapping a third region of the insulating layer. The plurality of first protruding electrodes is arranged at a first pitch, the plurality of second protruding electrodes is arranged at a second pitch, and the plurality of third protruding electrodes is arranged at a third pitch different from each of the first pitch and the second pitch.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230066512A1

    公开(公告)日：2023-03-02

    申请号：US17841196

    申请日：2022-06-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keita TSUCHIYA ,  Shuuichi KARIYAZAKI ,  Kazuhiro MITAMURA

    IPC: H01L23/498 ,  H01L23/367 ,  H01L23/66 ,  H01P3/08

    Abstract: A wiring substrate includes: a first insulating layer; a ground plane formed on the first insulating layer; a second insulating layer formed on the first insulating layer such that the ground plane is covered with the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer formed on the second insulating layer such that the first signal wiring is covered with the third insulating layer; and a second signal wiring formed on the third insulating layer and electrically connected with the first signal wiring. The first signal wiring is arranged in a region overlapping with a portion of a heat radiating plate. The second signal wiring is not arranged in the region. The ground plane has an opening portion located at a position overlapping with the first signal wiring. The opening portion is formed so as to extend along the first signal wiring.

    SEMICONDUCTOR DEVICE HAVING WIRING SUBSTRATE WITH LEAD-OUT WIRINGS
    3.
    发明公开
    SEMICONDUCTOR DEVICE HAVING WIRING SUBSTRATE WITH LEAD-OUT WIRINGS 审中-公开

    公开(公告)号：US20230154839A1

    公开(公告)日：2023-05-18

    申请号：US17529972

    申请日：2021-11-18

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keita TSUCHIYA ,  Shuuichi KARIYAZAKI

    IPC: H01L23/498

    CPC classification number: H01L23/49838 ,  H01L24/13

    Abstract: A semiconductor device includes a wiring substrate having: a first wiring layer having pads; and a second wiring layer having wirings and via-lands. The via-lands include: first-row via-lands connected to first-row pads of the pads, respectively; and second-row via-lands connected to the second-row pads of the pads, respectively. In the perspective plan view, the first-row via-lands have: first via-lands arranged such that a center of each of the first via-lands is shifted in a direction away from a first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad; and second via-lands arranged such that a center of each of the second via-lands arranged at a position closer to the first side than the first via-land. In the perspective plan view, the first and second via-lands are alternately arranged in a first direction along the first side.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190115295A1

    公开(公告)日：2019-04-18

    申请号：US16057724

    申请日：2018-08-07

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Shuuichi KARIYAZAKI ,  Keita TSUCHIYA ,  Yoshitaka OKAYASU ,  Wataru SHIROI

    IPC: H01L23/498 ,  H01L23/00

    Abstract: A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled.

    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240153854A1

    公开(公告)日：2024-05-09

    申请号：US18358400

    申请日：2023-07-25

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keita TSUCHIYA ,  Tatsuaki TSUKUDA

    IPC: H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

    Abstract: A semiconductor device includes a wiring substrate including a plurality of wiring layers, and a semiconductor chip including a first analog circuit. A power supply potential pattern capable of supplying a first power supply potential to the first analog circuit and a reference potential pattern capable of supplying a first reference potential to the first analog circuit are electrically connected with the first analog circuit. The power supply potential pattern is provided in a first wiring layer which is the nearest to a lower surface of the wiring substrate among the plurality of wiring layers. The reference potential pattern is provided in a second wiring layer which is the next nearest to the lower surface after the first wiring layer. The power supply potential pattern and the reference potential pattern extend in the same direction as each other while mutually overlapping with each other in transparent plan view.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220406700A1

    公开(公告)日：2022-12-22

    申请号：US17722823

    申请日：2022-04-18

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Nobuhiro KINOSHITA ,  Shuuichi KARIYAZAKI ,  Keita TSUCHIYA

    IPC: H01L23/498 ,  H01L23/66

    Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. Also, the first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. Also, the second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190198462A1

    公开(公告)日：2019-06-27

    申请号：US16175522

    申请日：2018-10-30

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kazuyuki NAKAGAWA ,  Keita TSUCHIYA ,  Yoshiaki SATO ,  Shuuichi KARIYAZAKI ,  Norio CHUJO ,  Masayoshi YAGYU ,  Yutaka UEMATSU

    IPC: H01L23/66 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00

    Abstract: A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180374788A1

    公开(公告)日：2018-12-27

    申请号：US16063280

    申请日：2016-02-10

    Applicant: Renesas Electronics Corporation

    Inventor： Kazuyuki NAKAGAWA ,  Katsushi TERAJIMA ,  Keita TSUCHIYA ,  Yoshiaki SATO ,  Hiroyuki UCHIDA ,  Yuji KAYASHIMA ,  Shuuichi KARIYAZAKI ,  Shinji BABA

    IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. In addition, the first terminal of the first semiconductor component is electrically connected to the wiring substrate via a first bump electrode without the first wiring member interposed therebetween.

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