公开(公告)号：US20160043036A1

公开(公告)日：2016-02-11

申请号：US14809070

申请日：2015-07-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi OGURA ,  Tatsuya USAMI ,  Satoshi KODAMA ,  Shuuichirou UENO ,  Satoshi ITOU ,  Takamasa ITOU

IPC: H01L23/532 ,  H01L49/02

CPC classification number: H01L23/53266 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76841 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductor provided in an interconnection layer is allowed to have a low resistance. An insulator film is provided over a substrate, and is comprised of SiO(1-x)Nx (where x>0.5 in an XRD analysis result). An interconnection is provided over the insulator film, and includes a first layer and a second layer. The first layer includes at least one of TiN, TaN, WN, and RuN. The second layer is provided over the first layer, and is formed of a material having a resistance lower than the first layer, for example, W.

Abstract translation: 设置在互连层中的导体允许具有低电阻。 绝缘膜设置在衬底上，由SiO（1-x）Nx（XRD分析结果中x> 0.5）组成。 在绝缘膜上设置互连，并且包括第一层和第二层。 第一层包括TiN，TaN，WN和RuN中的至少一种。 第二层设置在第一层之上，并且由具有低于第一层的电阻的材料形成，例如W.