公开(公告)号：US20170062446A1

公开(公告)日：2017-03-02

申请号：US15242489

申请日：2016-08-20

Applicant: Renesas Electronics Corporation

Inventor： Satoshi KODAMA ,  Eiji HASEGAWA

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

Abstract: An insulating film made of the same material as that of a gate insulating film is formed so as to cover one sidewall of a control gate on a conducting film for floating gate. By selectively removing the conducting film for floating gate with the insulating film as a mask, a floating gate is formed from the conducting film for floating gate, and a portion of the gate insulating film is exposed at the floating gate. A nitrogen introduced portion is formed by introducing nitrogen into the exposed portion of the gate insulating film. Then, the insulating film is removed to expose an upper surface of a lateral protrusion of the floating gate. An erase gate is formed so as to face the upper surface and a side surface of the lateral protrusion.

Abstract translation: 形成由与栅极绝缘膜相同的材料制成的绝缘膜，以覆盖用于浮动栅极的导电膜上的控制栅极的一个侧壁。 通过以绝缘膜为掩模选择性地去除浮栅用导电膜，由浮栅用导电膜形成浮栅，栅极绝缘膜的一部分在浮栅露出。 氮引入部分通过将氮引入到栅极绝缘膜的暴露部分中而形成。 然后，去除绝缘膜以露出浮动栅极的横向突起的上表面。 形成擦除门，以便面向横向突起的上表面和侧表面。

公开(公告)号：US20170330888A1

公开(公告)日：2017-11-16

申请号：US15664474

申请日：2017-07-31

Applicant: Renesas Electronics Corporation

Inventor： Satoshi KODAMA ,  Eiji HASEGAWA

IPC: H01L27/11521 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

Abstract: An insulating film made of the same material as that of a gate insulating film is formed so as to cover one sidewall of a control gate on a conducting film for floating gate. By selectively removing the conducting film for floating gate with the insulating film as a mask, a floating gate is formed from the conducting film for floating gate, and a portion of the gate insulating film is exposed at the floating gate. A nitrogen introduced portion is formed by introducing nitrogen into the exposed portion of the gate insulating film. Then, the insulating film is removed to expose an upper surface of a lateral protrusion of the floating gate. An erase gate is formed so as to face the upper surface and a side surface of the lateral protrusion.

公开(公告)号：US20160043036A1

公开(公告)日：2016-02-11

申请号：US14809070

申请日：2015-07-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi OGURA ,  Tatsuya USAMI ,  Satoshi KODAMA ,  Shuuichirou UENO ,  Satoshi ITOU ,  Takamasa ITOU

IPC: H01L23/532 ,  H01L49/02

CPC classification number: H01L23/53266 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76841 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductor provided in an interconnection layer is allowed to have a low resistance. An insulator film is provided over a substrate, and is comprised of SiO(1-x)Nx (where x>0.5 in an XRD analysis result). An interconnection is provided over the insulator film, and includes a first layer and a second layer. The first layer includes at least one of TiN, TaN, WN, and RuN. The second layer is provided over the first layer, and is formed of a material having a resistance lower than the first layer, for example, W.

Abstract translation: 设置在互连层中的导体允许具有低电阻。 绝缘膜设置在衬底上，由SiO（1-x）Nx（XRD分析结果中x> 0.5）组成。 在绝缘膜上设置互连，并且包括第一层和第二层。 第一层包括TiN，TaN，WN和RuN中的至少一种。 第二层设置在第一层之上，并且由具有低于第一层的电阻的材料形成，例如W.