公开(公告)号：US20180372950A1

公开(公告)日：2018-12-27

申请号：US15977479

申请日：2018-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI

IPC: G02B6/12

CPC classification number: G02B6/12 ,  G02B2006/12061 ,  G02B2006/12083 ,  G02B2006/12166 ,  G02F1/025 ,  H01L23/345

Abstract: An object of the present invention is to reduce the manufacturing cost of a semiconductor device. A semiconductor device includes a SOI substrate that has an optical waveguide including a semiconductor layer. The optical waveguide is covered with an interlayer insulating film. Wiring parts are formed on the interlayer insulating film. Moreover, a thin film part having a smaller thickness than the wiring parts is formed above the optical waveguide and is integrated with the wiring parts.

公开(公告)号：US20170045683A1

公开(公告)日：2017-02-16

申请号：US15201479

申请日：2016-07-03

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI

IPC: G02B6/122 ,  G02F1/025 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B2006/12061 ,  G02F1/025 ,  G02F2202/104

Abstract: Good optical properties can be achieved in an optical waveguide made of polycrystalline silicon.A semiconductor layer that constitutes each of a first optical signal line, a second optical signal line, a grating coupler, an optical modulator, and a p-type layer of a germanium optical receiver is formed by a polycrystalline silicon film. Crystal grains of polycrystalline silicon exposed on an upper surface of the semiconductor layer include crystal grains having flat surfaces parallel to a first main surface of a semiconductor substrate, and crystal grains of polycrystalline silicon exposed on side surfaces (including side surfaces of a protrusion of a protruding portion) of the semiconductor layer include crystal grains having flat surfaces perpendicular to the first main surface of the semiconductor substrate.

Abstract translation: 通过多晶硅膜形成构成锗光接收器的第一光信号线，第二光信号线，光栅耦合器，光调制器和p型层中的每一个的半导体层。 暴露在半导体层的上表面上的多晶硅的晶粒包括具有平行于半导体衬底的第一主表面的平坦表面的晶粒和暴露于侧表面（包括 突出部分）包括具有与半导体衬底的第一主表面垂直的平坦表面的晶粒。

公开(公告)号：US20230411233A1

公开(公告)日：2023-12-21

申请号：US18304880

申请日：2023-04-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L23/291 ,  H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L21/56 ,  H01L2224/03614 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05561 ,  H01L2224/05567 ,  H01L2224/06155 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L24/45

Abstract: Wirings next to each other spaced apart by a first distance are formed in the uppermost layer of a multilayer wiring layer formed on a semiconductor substrate. A protective film covers upper surfaces and side surfaces of the wirings. The protective films formed on the side surfaces of the wirings are spaced apart from each other. The protective film is formed of an inorganic dielectric film. A thickness of the protective film formed on the upper surfaces of the wirings is larger than a thickness of the protective film formed on the side surfaces of the wirings.

公开(公告)号：US20190237361A1

公开(公告)日：2019-08-01

申请号：US16242686

申请日：2019-01-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/32135 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53295

Abstract: In a semiconductor device, among first wirings, second wirings and a third wiring formed in the same wiring layer, the first wirings having small wiring width are each composed of a stacked film of a first barrier conductor film, a first conductor film made of a material mainly containing a metal element whose mean free path of electrons is smaller than that of copper, and a second barrier conductor film. Also, among the first wirings, the second wirings and the third wiring formed in the same wiring layer, the second wirings and the third wiring having large wiring width are each composed of a stacked film of a third barrier conductor film and a second conductor film made of copper.

公开(公告)号：US20180350760A1

公开(公告)日：2018-12-06

申请号：US15987169

申请日：2018-05-23

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI

IPC: H01L23/00 ,  H01L23/522

Abstract: A semiconductor device and a manufacturing method thereof according to the present invention include: a first pad electrode formed in an uppermost wiring layer of a multilayer wiring layer; a first insulating film formed on the first pad electrode; and a first organic insulating film formed over the first insulating film. Also, the semiconductor device and the manufacturing method thereof include: a barrier metal film formed on the first organic insulating film and connected to the first pad electrode; and a conductive film formed on the barrier metal film. Then, a second insulating film made of an inorganic material is formed on an upper surface of the first organic insulating film between the barrier metal film and the first organic insulating film.

公开(公告)号：US20170317221A1

公开(公告)日：2017-11-02

申请号：US15469455

申请日：2017-03-24

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya USAMI

IPC: H01L31/0352 ,  H01L31/028 ,  H01L31/109 ,  H01L31/18

CPC classification number: H01L31/03529 ,  G02B6/00 ,  G02B6/12004 ,  H01L31/0224 ,  H01L31/028 ,  H01L31/035281 ,  H01L31/105 ,  H01L31/109 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547

Abstract: There is to provide a semiconductor device including a light receiving element capable of reducing the manufacturing cost and improving the optical performance of the light receiving element. For example, a p type germanium layer, an intrinsic germanium layer, and an n type germanium layer forming the structure body of a Ge photodiode are formed according to a continuous selective epitaxial growth. An insulating film having an opening portion is formed on the silicon layer of a SOI substrate, and an intrinsic germanium layer is formed bulging from the opening portion to above the insulating film. In short, by using the insulating film having the opening portion, the cross section of the intrinsic germanium layer is formed into a mushroom shape.

公开(公告)号：US20160043036A1

公开(公告)日：2016-02-11

申请号：US14809070

申请日：2015-07-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi OGURA ,  Tatsuya USAMI ,  Satoshi KODAMA ,  Shuuichirou UENO ,  Satoshi ITOU ,  Takamasa ITOU

IPC: H01L23/532 ,  H01L49/02

CPC classification number: H01L23/53266 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76841 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductor provided in an interconnection layer is allowed to have a low resistance. An insulator film is provided over a substrate, and is comprised of SiO(1-x)Nx (where x>0.5 in an XRD analysis result). An interconnection is provided over the insulator film, and includes a first layer and a second layer. The first layer includes at least one of TiN, TaN, WN, and RuN. The second layer is provided over the first layer, and is formed of a material having a resistance lower than the first layer, for example, W.

Abstract translation: 设置在互连层中的导体允许具有低电阻。 绝缘膜设置在衬底上，由SiO（1-x）Nx（XRD分析结果中x> 0.5）组成。 在绝缘膜上设置互连，并且包括第一层和第二层。 第一层包括TiN，TaN，WN和RuN中的至少一种。 第二层设置在第一层之上，并且由具有低于第一层的电阻的材料形成，例如W.

公开(公告)号：US20230103256A1

公开(公告)日：2023-03-30

申请号：US17892626

申请日：2022-08-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI ,  Yoshiki MARUYAMA ,  Yuki MURAYAMA ,  Yuji ISHII

IPC: H01L23/00

Abstract: A semiconductor device includes: a semiconductor substrate having first and second main surfaces; interlayer insulating films laminated on the first main surface in a thickness direction from the second main surface toward the first main surface; a top wiring arranged on a top interlayer insulating film of the plurality of interlayer insulating films, which is provided farthest from the first main surface in the thickness direction; and a passivation film arranged on the top interlayer insulating film so as to cover the top wiring. The top wiring includes a first wiring portion and a second wiring portion that extend in a first direction in plan view and are adjacent to each other in a second direction orthogonal to the first direction. A first distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction is 2.7 μm or more.

公开(公告)号：US20220013481A1

公开(公告)日：2022-01-13

申请号：US16927331

申请日：2020-07-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI

IPC: H01L23/00 ,  H01L23/31

Abstract: A groove is formed between an inner peripheral edge of an opening of a pad electrode and an outer peripheral edge of a bonding region located inside the pad electrode in plan view.

公开(公告)号：US20190198468A1

公开(公告)日：2019-06-27

申请号：US16183359

申请日：2018-11-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI

IPC: H01L23/00 ,  H01L23/532

Abstract: Reliability of a semiconductor device is improved. A first pad electrode is formed in an uppermost layer of a multilayer wiring layer, an insulating film of a non-organic material is formed over the first pad electrode, and an organic insulating film is formed over the insulating film. In the organic insulating film, an opening reaching the first pad electrode and a groove reaching the insulating film are formed. Over the organic insulating film, a plurality of re-wirings each having a barrier metal film and a conductive film are formed. In a plan view, the groove is formed in an area between the re-wirings. At the same time, a width of the groove is smaller than a width of a first portion or a width of a second portion of the re-wirings, respectively, neighboring to each other and extending in a first direction.