公开(公告)号：US20240363500A1

公开(公告)日：2024-10-31

申请号：US18307405

申请日：2023-04-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshimasa UCHINUMA ,  Takehiro UEDA

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/4952 ,  H01L23/49568 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device includes a first source electrode coupled to a first source terminal by a connection portion and having first and second slits on two opposite sides, a second source electrode coupled to a second source terminal, a Kelvin pad formed independently of the first source electrode, a power MOSFET coupled between the first source electrode and a drain terminal, a sense MOSFET coupled between the second source electrode and the drain terminal, a first wire coupled between a first source potential extraction port set at the first slit and the Kelvin pad, a second wire coupled between a second source potential extraction port set at the second slit and the Kelvin pad, wherein the connection portion has third and fourth slits corresponding to the first and second slits.

公开(公告)号：US20220115306A1

公开(公告)日：2022-04-14

申请号：US17068446

申请日：2020-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshimasa UCHINUMA ,  Yusuke OJIMA

IPC: H01L23/495 ,  H01L23/31

Abstract: A semiconductor device includes a semiconductor chip, first and second source terminals and a Kelvin terminal, wherein the semiconductor chip includes a first source electrode coupled to the first source terminal through a first connecting portion, a second source electrode coupled to the second source terminal through a second connecting portion, a Kelvin pad coupled to the Kelvin terminal and formed independently of the first source electrode, a power MOSFET that has a source coupled to the first source electrode, a sense MOSFET that has a source coupled to the second source electrode, a source pad formed on a portion of the first source electrode and coupled to the first connecting portion, a plurality of source potential extraction ports formed around a connection point between the first connecting portion and the source pad and a plurality of wires coupled between the source potential extraction ports and the Kelvin pad.

公开(公告)号：US20160163698A1

公开(公告)日：2016-06-09

申请号：US15044875

申请日：2016-02-16

Applicant: Renesas Electronics Corporation

Inventor： Junichi NITA ,  Kazutaka SUZUKI ,  Takahiro KORENARI ,  Yoshimasa UCHINUMA

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/423 ,  H01L23/535

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0865 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.

Abstract translation: 半导体装置包括第一区域，第一晶体管形成在第一区域的两个或更多分割区域中，第二区域，第二晶体管形成在第二区域的两个或更多个分割区域中。 第二区域的面积数大于第一区域的面积数，第一区域和第二区域的分割区域交替排列，第一晶体管的栅极焊盘和第二区域的栅极焊盘 晶体管形成在第二区域中。