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公开(公告)号：US10268619B2
公开(公告)日：2019-04-23
申请号：US15169275
申请日：2016-05-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Kishore Kasamsetty
Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.
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公开(公告)号：US20160275033A1
公开(公告)日：2016-09-22
申请号：US15169275
申请日：2016-05-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Kishore Kasamsetty
CPC classification number: G06F13/4022 , G06F3/061 , G06F3/0647 , G06F3/0683 , G06F12/00 , G06F12/02 , G06F13/1657 , G06F13/1668 , G06F13/4282 , G11C5/02
Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.
Abstract translation: 多芯片封装包括形成有多个存储器控制器电路的逻辑集成电路（IC）管芯，第一存储器IC管芯和第二存储器IC管芯。 第二存储器IC管芯安装到第一存储器IC管芯。 第一存储器IC管芯和逻辑IC管芯彼此安装。 逻辑IC芯片包括用于耦合到多个串行链路的串行链路接口。 第一存储器管芯包括由多个存储器控制器电路中的第一个访问的第一存储器组和由多个存储器控制器电路中的第二存储器控制器电路访问的第二存储器组。
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Patent Agency Ranking
公开(公告)号：US11194749B2
公开(公告)日：2021-12-07
申请号：US16365535
申请日：2019-03-26
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Kishore Kasamsetty
Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.
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公开(公告)号：US20220164305A1
公开(公告)日：2022-05-26
申请号：US17540909
申请日：2021-12-02
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Kishore Kasamsetty
Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.
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公开(公告)号：US20190317912A1
公开(公告)日：2019-10-17
申请号：US16365535
申请日：2019-03-26
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Kishore Kasamsetty
Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.
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公开(公告)号：US09355021B2
公开(公告)日：2016-05-31
申请号：US13909339
申请日：2013-06-04
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Kishore Kasamsetty
CPC classification number: G06F13/4022 , G06F3/061 , G06F3/0647 , G06F3/0683 , G06F12/00 , G06F12/02 , G06F13/1657 , G06F13/1668 , G06F13/4282 , G11C5/02
Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.
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公开(公告)号：US20130339631A1
公开(公告)日：2013-12-19
申请号：US13909339
申请日：2013-06-04
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Kishore Kasamsetty
IPC: G06F12/00
CPC classification number: G06F13/4022 , G06F3/061 , G06F3/0647 , G06F3/0683 , G06F12/00 , G06F12/02 , G06F13/1657 , G06F13/1668 , G06F13/4282 , G11C5/02
Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.
Abstract translation: 在数据处理系统中，缓冲器集成电路（IC）装置包括多个控制接口，多个存储器接口和切换电路，以根据路径选择值将每个控制接口同时耦合到相应的一个存储器接口。 多个请求者IC设备分别耦合到控制接口，并且多个存储器IC设备分别耦合到存储器接口。
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