公开(公告)号：US20220182267A1

公开(公告)日：2022-06-09

申请号：US17532865

申请日：2021-11-22

Applicant: Rambus Inc.

Inventor： Nanyan Wang ,  Marcus van Ierssel

IPC: H04L25/49 ,  H03L7/08 ,  H04L27/06 ,  H04L7/033

Abstract: A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called “edge lock,” rather than on the symbols themselves. A transition-type detector senses the edge-lock condition and unlocks the CDR, which can then realign the clock signal, this time on the symbols rather than the inter-symbol edges. The receiver can also respond to the edge-lock condition by kick-starting a shift of symbol-decision threshold that helps the CDR settle more quickly on correct symbol-decision thresholds.

公开(公告)号：US20170093558A1

公开(公告)日：2017-03-30

申请号：US14871719

申请日：2015-09-30

Applicant: Rambus Inc.

Inventor： Mehrdad Ramezani ,  David J. Cassan ,  Christopher D. Holdenried ,  Sang-Wook Paul Park ,  Marcus van Ierssel

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

CPC classification number: H04L7/0087 ,  H03L7/081 ,  H04L7/0029 ,  H04L7/0079 ,  H04L7/0331 ,  H04L7/0337 ,  H04L25/03057

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

公开(公告)号：US11477059B2

公开(公告)日：2022-10-18

申请号：US17532865

申请日：2021-11-22

Applicant: Rambus Inc.

Inventor： Nanyan Wang ,  Marcus van Ierssel

IPC: H04L25/49 ,  H04L7/033 ,  H04L27/06 ,  H03L7/08

Abstract: A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called “edge lock,” rather than on the symbols themselves. A transition-type detector senses the edge-lock condition and unlocks the CDR, which can then realign the clock signal, this time on the symbols rather than the inter-symbol edges. The receiver can also respond to the edge-lock condition by kick-starting a shift of symbol-decision threshold that helps the CDR settle more quickly on correct symbol-decision thresholds.

公开(公告)号：US20220329247A1

公开(公告)日：2022-10-13

申请号：US17719974

申请日：2022-04-13

Applicant: Rambus Inc.

Inventor： Marcus van Ierssel ,  Prabhnoor Singh Kainth ,  Nanyan Wang

IPC: H03L7/107 ,  H04L7/00 ,  H04L7/02 ,  H03L7/08 ,  H03L7/093

Abstract: A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaption circuitry uses the measure to adjust the clock-recovery circuity in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.

公开(公告)号：US09716582B2

公开(公告)日：2017-07-25

申请号：US14871719

申请日：2015-09-30

Applicant: Rambus Inc.

Inventor： Mehrdad Ramezani ,  David J. Cassan ,  Christopher D. Holdenried ,  Sang-Wook Paul Park ,  Marcus van Ierssel

IPC: H04L7/00 ,  H04L25/03 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H03L7/081 ,  H04L7/0029 ,  H04L7/0079 ,  H04L7/0331 ,  H04L7/0337 ,  H04L25/03057

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.