公开(公告)号：US20170346618A1

公开(公告)日：2017-11-30

申请号：US15629453

申请日：2017-06-21

Applicant: Rambus Inc.

Inventor： Mehrdad Ramezani ,  David J. Cassan ,  Christopher D. Holdenried ,  Sang-Wook Paul Park ,  Marcus Van Ierssel

IPC: H04L7/00 ,  H04L7/033 ,  H03L7/081 ,  H04L25/03

CPC classification number: H04L7/0087 ,  H03L7/081 ,  H04L7/0029 ,  H04L7/0079 ,  H04L7/0331 ,  H04L7/0337 ,  H04L25/03057

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

公开(公告)号：US09716582B2

公开(公告)日：2017-07-25

申请号：US14871719

申请日：2015-09-30

Applicant: Rambus Inc.

Inventor： Mehrdad Ramezani ,  David J. Cassan ,  Christopher D. Holdenried ,  Sang-Wook Paul Park ,  Marcus van Ierssel

IPC: H04L7/00 ,  H04L25/03 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H03L7/081 ,  H04L7/0029 ,  H04L7/0079 ,  H04L7/0331 ,  H04L7/0337 ,  H04L25/03057

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

公开(公告)号：US20170093558A1

公开(公告)日：2017-03-30

申请号：US14871719

申请日：2015-09-30

Applicant: Rambus Inc.

Inventor： Mehrdad Ramezani ,  David J. Cassan ,  Christopher D. Holdenried ,  Sang-Wook Paul Park ,  Marcus van Ierssel

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

CPC classification number: H04L7/0087 ,  H03L7/081 ,  H04L7/0029 ,  H04L7/0079 ,  H04L7/0331 ,  H04L7/0337 ,  H04L25/03057

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

公开(公告)号：US10211972B2

公开(公告)日：2019-02-19

申请号：US15629453

申请日：2017-06-21

Applicant: Rambus Inc.

Inventor： Mehrdad Ramezani ,  David J. Cassan ,  Christopher D. Holdenried ,  Sang-Wook Paul Park ,  Marcus Van Ierssel

IPC: H04L7/00 ,  H04L25/03 ,  H03L7/081 ,  H04L7/033

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.